From: Biju Das <biju.das.jz@bp.renesas.com>
Add documentation for the serial communication interface (RSCI) found on
the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
(2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
* Dropped 1st and 3rd items from clk-names and added minItems for the
range.
* Added minItems for clk and clk-names for RZ/T2H as the range is 2-3
* Added maxItems for clk and clk-names for RZ/G3E as the range is 5-6
* Retained the tag as it is trivial change.
v1->v2:
* Updated commit message
* Added resets:false for non RZ/G3E SoCs.
---
.../bindings/serial/renesas,rsci.yaml | 85 ++++++++++++++++---
1 file changed, 74 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index 6b1f827a335b..1a35d6fa67b1 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -10,17 +10,16 @@ maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
-allOf:
- - $ref: serial.yaml#
-
properties:
compatible:
oneOf:
- - items:
- - const: renesas,r9a09g087-rsci # RZ/N2H
- - const: renesas,r9a09g077-rsci # RZ/T2H
+ - enum:
+ - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
+ - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
+ - renesas,r9a09g077-rsci # RZ/T2H
- items:
+ - const: renesas,r9a09g087-rsci # RZ/N2H
- const: renesas,r9a09g077-rsci # RZ/T2H
reg:
@@ -42,14 +41,36 @@ properties:
clocks:
minItems: 2
- maxItems: 3
+ maxItems: 6
clock-names:
- minItems: 2
+ oneOf:
+ - items:
+ - const: operation
+ - const: bus
+ - const: sck # optional external clock input
+
+ minItems: 2
+
+ - items:
+ - const: bus
+ - const: tclk
+ - const: tclk_div64
+ - const: tclk_div16
+ - const: tclk_div4
+ - const: sck # optional external clock input
+
+ minItems: 5
+
+ resets:
+ items:
+ - description: Input for resetting the APB clock
+ - description: Input for resetting TCLK
+
+ reset-names:
items:
- - const: operation
- - const: bus
- - const: sck # optional external clock input
+ - const: presetn
+ - const: tresetn
power-domains:
maxItems: 1
@@ -62,6 +83,48 @@ required:
- clock-names
- power-domains
+allOf:
+ - $ref: serial.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-rsci
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a09g047-rsci
+ - renesas,r9a09g047-rscif
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 6
+
+ clock-names:
+ minItems: 5
+ maxItems: 6
+
+ required:
+ - resets
+ - reset-names
+ else:
+ properties:
+ resets: false
+
unevaluatedProperties: false
examples:
--
2.43.0