From: Biju Das <biju.das.jz@bp.renesas.com>
Add support for 32 bits sample format width for RZ/G2L SoCs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Dropped checking 32-bit sample width in rz_ssi_dma_slave_config() as it
is taken care by restructuring the test.
---
sound/soc/renesas/rz-ssi.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/sound/soc/renesas/rz-ssi.c b/sound/soc/renesas/rz-ssi.c
index 3ec7c9875b43..5909778a6a70 100644
--- a/sound/soc/renesas/rz-ssi.c
+++ b/sound/soc/renesas/rz-ssi.c
@@ -75,7 +75,8 @@
#define PREALLOC_BUFFER_MAX (SZ_32K)
#define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */
-#define SSI_FMTS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
+#define SSI_FMTS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
#define SSI_CHAN_MIN 2
#define SSI_CHAN_MAX 2
#define SSI_FIFO_DEPTH 32
@@ -295,7 +296,7 @@ static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate,
}
/*
- * DWL: Data Word Length = {16, 24} bits
+ * DWL: Data Word Length = {16, 24, 32} bits
* SWL: System Word Length = 32 bits
*/
ssicr |= SSICR_CKDV(clk_ckdv);
@@ -306,6 +307,9 @@ static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate,
case 24:
ssicr |= SSICR_DWL(5) | SSICR_PDTA;
break;
+ case 32:
+ ssicr |= SSICR_DWL(6);
+ break;
default:
dev_err(ssi->dev, "Not support %u data width",
ssi->hw_params_cache.sample_width);
@@ -1016,7 +1020,7 @@ static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream,
unsigned int rate = params_rate(params);
int ret;
- if (!(sample_bits == 16 || sample_bits == 24)) {
+ if (!(sample_bits == 16 || sample_bits == 24 || sample_bits == 32)) {
dev_err(ssi->dev, "Unsupported sample width: %d\n",
sample_bits);
return -EINVAL;
--
2.43.0