Prepare struct operand for hosting AVX registers. Remove the
existing, incomplete code that placed the Avx flag in the operand
alignment field, and repurpose the name for a separate bit that
indicates:
- after decode, whether an instruction supports the VEX prefix;
- before writeback, that the instruction did have the VEX prefix and
therefore 1) it can have op_bytes == 32; 2) t should clear high
bytes of XMM registers.
Right now the bit will never be set and the patch has no intended
functional change. However, this is actually more vexing than the
decoder changes itself, and therefore worth separating.
Co-developed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
arch/x86/kvm/emulate.c | 58 ++++++++++++++++++++++++++---------
arch/x86/kvm/fpu.h | 62 ++++++++++++++++++++++++++++++++++++++
arch/x86/kvm/kvm_emulate.h | 7 +++--
3 files changed, 110 insertions(+), 17 deletions(-)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 6c8d3f786e74..94dc8a61965b 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -141,6 +141,7 @@
#define No64 (1<<28) /* Instruction generates #UD in 64-bit mode */
#define PageTable (1 << 29) /* instruction used to write page table */
#define NotImpl (1 << 30) /* instruction is not implemented */
+#define Avx ((u64)1 << 31) /* Instruction uses VEX prefix */
#define Src2Shift (32) /* Source 2 operand type at bits 32-36 */
#define Src2None (OpNone << Src2Shift)
#define Src2Mem (OpMem << Src2Shift)
@@ -157,12 +158,11 @@
#define Src2Mask (OpMask << Src2Shift)
/* free: 37-39 */
#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
-#define AlignMask ((u64)7 << 41) /* Memory alignment requirement at bits 41-43 */
+#define AlignMask ((u64)3 << 41) /* Memory alignment requirement at bits 41-42 */
#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */
-#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */
-#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
-/* free: 44 */
+#define Aligned16 ((u64)3 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
+/* free: 43-44 */
#define NoWrite ((u64)1 << 45) /* No writeback */
#define SrcWrite ((u64)1 << 46) /* Write back src operand */
#define NoMod ((u64)1 << 47) /* Mod field is ignored */
@@ -618,7 +618,6 @@ static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
switch (alignment) {
case Unaligned:
- case Avx:
return 1;
case Aligned16:
return 16;
@@ -1075,7 +1074,14 @@ static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
static void __decode_register_operand(struct x86_emulate_ctxt *ctxt,
struct operand *op, int reg)
{
- if (ctxt->d & Sse) {
+ if ((ctxt->d & Avx) && ctxt->op_bytes == 32) {
+ op->type = OP_YMM;
+ op->bytes = 32;
+ op->addr.xmm = reg;
+ kvm_read_avx_reg(reg, &op->vec_val2);
+ return;
+ }
+ if (ctxt->d & (Avx|Sse)) {
op->type = OP_XMM;
op->bytes = 16;
op->addr.xmm = reg;
@@ -1767,7 +1773,15 @@ static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
op->data,
op->bytes * op->count);
case OP_XMM:
- kvm_write_sse_reg(op->addr.xmm, &op->vec_val);
+ if (!(ctxt->d & Avx)) {
+ kvm_write_sse_reg(op->addr.xmm, &op->vec_val);
+ break;
+ }
+ /* full YMM write but with high bytes cleared */
+ memset(op->valptr + 16, 0, 16);
+ fallthrough;
+ case OP_YMM:
+ kvm_write_avx_reg(op->addr.xmm, &op->vec_val2);
break;
case OP_MM:
kvm_write_mmx_reg(op->addr.mm, &op->mm_val);
@@ -4861,9 +4875,8 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int
ctxt->op_bytes = 8; /* REX.W */
/* Opcode byte(s). */
- opcode = opcode_table[ctxt->b];
- /* Two-byte opcode? */
if (ctxt->b == 0x0f) {
+ /* Two- or three-byte opcode */
ctxt->opcode_len = 2;
ctxt->b = insn_fetch(u8, ctxt);
opcode = twobyte_table[ctxt->b];
@@ -4874,6 +4887,9 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int
ctxt->b = insn_fetch(u8, ctxt);
opcode = opcode_map_0f_38[ctxt->b];
}
+ } else {
+ /* Opcode byte(s). */
+ opcode = opcode_table[ctxt->b];
}
ctxt->d = opcode.flags;
@@ -5022,7 +5038,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int
ctxt->op_bytes = 4;
if (ctxt->d & Sse)
- ctxt->op_bytes = 16;
+ ctxt->op_bytes = 16, ctxt->d &= ~Avx;
else if (ctxt->d & Mmx)
ctxt->op_bytes = 8;
}
@@ -5154,20 +5170,34 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, bool check_intercepts)
}
if (unlikely(ctxt->d &
- (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
+ (No64|Undefined|Avx|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
(ctxt->d & Undefined)) {
rc = emulate_ud(ctxt);
goto done;
}
- if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
- || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
+ if ((ctxt->d & (Avx|Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) {
rc = emulate_ud(ctxt);
goto done;
}
- if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
+ if (ctxt->d & Avx) {
+ u64 xcr = 0;
+ if (!(ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE)
+ || ops->get_xcr(ctxt, 0, &xcr)
+ || !(xcr & XFEATURE_MASK_YMM)) {
+ rc = emulate_ud(ctxt);
+ goto done;
+ }
+ } else if (ctxt->d & Sse) {
+ if (!(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR)) {
+ rc = emulate_ud(ctxt);
+ goto done;
+ }
+ }
+
+ if ((ctxt->d & (Avx|Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
rc = emulate_nm(ctxt);
goto done;
}
diff --git a/arch/x86/kvm/fpu.h b/arch/x86/kvm/fpu.h
index 3ba12888bf66..9bc08c3c53f5 100644
--- a/arch/x86/kvm/fpu.h
+++ b/arch/x86/kvm/fpu.h
@@ -15,6 +15,54 @@ typedef u32 __attribute__((vector_size(16))) sse128_t;
#define sse128_l3(x) ({ __sse128_u t; t.vec = x; t.as_u32[3]; })
#define sse128(lo, hi) ({ __sse128_u t; t.as_u64[0] = lo; t.as_u64[1] = hi; t.vec; })
+typedef u32 __attribute__((vector_size(32))) avx256_t;
+
+static inline void _kvm_read_avx_reg(int reg, avx256_t *data)
+{
+ switch (reg) {
+ case 0: asm("vmovdqa %%ymm0, %0" : "=m"(*data)); break;
+ case 1: asm("vmovdqa %%ymm1, %0" : "=m"(*data)); break;
+ case 2: asm("vmovdqa %%ymm2, %0" : "=m"(*data)); break;
+ case 3: asm("vmovdqa %%ymm3, %0" : "=m"(*data)); break;
+ case 4: asm("vmovdqa %%ymm4, %0" : "=m"(*data)); break;
+ case 5: asm("vmovdqa %%ymm5, %0" : "=m"(*data)); break;
+ case 6: asm("vmovdqa %%ymm6, %0" : "=m"(*data)); break;
+ case 7: asm("vmovdqa %%ymm7, %0" : "=m"(*data)); break;
+ case 8: asm("vmovdqa %%ymm8, %0" : "=m"(*data)); break;
+ case 9: asm("vmovdqa %%ymm9, %0" : "=m"(*data)); break;
+ case 10: asm("vmovdqa %%ymm10, %0" : "=m"(*data)); break;
+ case 11: asm("vmovdqa %%ymm11, %0" : "=m"(*data)); break;
+ case 12: asm("vmovdqa %%ymm12, %0" : "=m"(*data)); break;
+ case 13: asm("vmovdqa %%ymm13, %0" : "=m"(*data)); break;
+ case 14: asm("vmovdqa %%ymm14, %0" : "=m"(*data)); break;
+ case 15: asm("vmovdqa %%ymm15, %0" : "=m"(*data)); break;
+ default: BUG();
+ }
+}
+
+static inline void _kvm_write_avx_reg(int reg, const avx256_t *data)
+{
+ switch (reg) {
+ case 0: asm("vmovdqa %0, %%ymm0" : : "m"(*data)); break;
+ case 1: asm("vmovdqa %0, %%ymm1" : : "m"(*data)); break;
+ case 2: asm("vmovdqa %0, %%ymm2" : : "m"(*data)); break;
+ case 3: asm("vmovdqa %0, %%ymm3" : : "m"(*data)); break;
+ case 4: asm("vmovdqa %0, %%ymm4" : : "m"(*data)); break;
+ case 5: asm("vmovdqa %0, %%ymm5" : : "m"(*data)); break;
+ case 6: asm("vmovdqa %0, %%ymm6" : : "m"(*data)); break;
+ case 7: asm("vmovdqa %0, %%ymm7" : : "m"(*data)); break;
+ case 8: asm("vmovdqa %0, %%ymm8" : : "m"(*data)); break;
+ case 9: asm("vmovdqa %0, %%ymm9" : : "m"(*data)); break;
+ case 10: asm("vmovdqa %0, %%ymm10" : : "m"(*data)); break;
+ case 11: asm("vmovdqa %0, %%ymm11" : : "m"(*data)); break;
+ case 12: asm("vmovdqa %0, %%ymm12" : : "m"(*data)); break;
+ case 13: asm("vmovdqa %0, %%ymm13" : : "m"(*data)); break;
+ case 14: asm("vmovdqa %0, %%ymm14" : : "m"(*data)); break;
+ case 15: asm("vmovdqa %0, %%ymm15" : : "m"(*data)); break;
+ default: BUG();
+ }
+}
+
static inline void _kvm_read_sse_reg(int reg, sse128_t *data)
{
switch (reg) {
@@ -109,6 +157,20 @@ static inline void kvm_fpu_put(void)
fpregs_unlock();
}
+static inline void kvm_read_avx_reg(int reg, avx256_t *data)
+{
+ kvm_fpu_get();
+ _kvm_read_avx_reg(reg, data);
+ kvm_fpu_put();
+}
+
+static inline void kvm_write_avx_reg(int reg, const avx256_t *data)
+{
+ kvm_fpu_get();
+ _kvm_write_avx_reg(reg, data);
+ kvm_fpu_put();
+}
+
static inline void kvm_read_sse_reg(int reg, sse128_t *data)
{
kvm_fpu_get();
diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h
index 5f9d69c64cd5..c526f46f5595 100644
--- a/arch/x86/kvm/kvm_emulate.h
+++ b/arch/x86/kvm/kvm_emulate.h
@@ -249,7 +249,7 @@ struct x86_emulate_ops {
/* Type, address-of, and value of an instruction's operand. */
struct operand {
- enum { OP_REG, OP_MEM, OP_MEM_STR, OP_IMM, OP_XMM, OP_MM, OP_NONE } type;
+ enum { OP_REG, OP_MEM, OP_MEM_STR, OP_IMM, OP_XMM, OP_YMM, OP_MM, OP_NONE } type;
unsigned int bytes;
unsigned int count;
union {
@@ -268,11 +268,12 @@ struct operand {
union {
unsigned long val;
u64 val64;
- char valptr[sizeof(sse128_t)];
+ char valptr[sizeof(avx256_t)];
sse128_t vec_val;
+ avx256_t vec_val2;
u64 mm_val;
void *data;
- };
+ } __aligned(32);
};
#define X86_MAX_INSTRUCTION_LENGTH 15
--
2.43.5Hi Paolo,
kernel test robot noticed the following build errors:
[auto build test ERROR on v6.18-rc5]
[also build test ERROR on linus/master next-20251114]
[cannot apply to kvm/queue kvm/next mst-vhost/linux-next kvm/linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Paolo-Bonzini/KVM-emulate-add-MOVNTDQA/20251114-084216
base: v6.18-rc5
patch link: https://lore.kernel.org/r/20251114003633.60689-8-pbonzini%40redhat.com
patch subject: [PATCH 07/10] KVM: emulate: add AVX support to register fetch and writeback
config: i386-buildonly-randconfig-006-20251114 (https://download.01.org/0day-ci/archive/20251115/202511150213.HaLLVfkt-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251115/202511150213.HaLLVfkt-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511150213.HaLLVfkt-lkp@intel.com/
All errors (new ones prefixed by >>):
arch/x86/kvm/fpu.h: Assembler messages:
>> arch/x86/kvm/fpu.h:37: Error: bad register name `%ymm14'
>> arch/x86/kvm/fpu.h:36: Error: bad register name `%ymm13'
>> arch/x86/kvm/fpu.h:38: Error: bad register name `%ymm15'
>> arch/x86/kvm/fpu.h:35: Error: bad register name `%ymm12'
>> arch/x86/kvm/fpu.h:34: Error: bad register name `%ymm11'
>> arch/x86/kvm/fpu.h:33: Error: bad register name `%ymm10'
>> arch/x86/kvm/fpu.h:32: Error: bad register name `%ymm9'
>> arch/x86/kvm/fpu.h:31: Error: bad register name `%ymm8'
arch/x86/kvm/fpu.h:58: Error: bad register name `%ymm12'
arch/x86/kvm/fpu.h:59: Error: bad register name `%ymm13'
arch/x86/kvm/fpu.h:54: Error: bad register name `%ymm8'
arch/x86/kvm/fpu.h:55: Error: bad register name `%ymm9'
arch/x86/kvm/fpu.h:56: Error: bad register name `%ymm10'
arch/x86/kvm/fpu.h:57: Error: bad register name `%ymm11'
arch/x86/kvm/fpu.h:61: Error: bad register name `%ymm15'
arch/x86/kvm/fpu.h:60: Error: bad register name `%ymm14'
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for I2C_K1
Depends on [n]: I2C [=y] && HAS_IOMEM [=y] && (ARCH_SPACEMIT || COMPILE_TEST [=y]) && OF [=n]
Selected by [y]:
- MFD_SPACEMIT_P1 [=y] && HAS_IOMEM [=y] && (ARCH_SPACEMIT || COMPILE_TEST [=y]) && I2C [=y]
vim +37 arch/x86/kvm/fpu.h
19
20 static inline void _kvm_read_avx_reg(int reg, avx256_t *data)
21 {
22 switch (reg) {
23 case 0: asm("vmovdqa %%ymm0, %0" : "=m"(*data)); break;
24 case 1: asm("vmovdqa %%ymm1, %0" : "=m"(*data)); break;
25 case 2: asm("vmovdqa %%ymm2, %0" : "=m"(*data)); break;
26 case 3: asm("vmovdqa %%ymm3, %0" : "=m"(*data)); break;
27 case 4: asm("vmovdqa %%ymm4, %0" : "=m"(*data)); break;
28 case 5: asm("vmovdqa %%ymm5, %0" : "=m"(*data)); break;
29 case 6: asm("vmovdqa %%ymm6, %0" : "=m"(*data)); break;
30 case 7: asm("vmovdqa %%ymm7, %0" : "=m"(*data)); break;
> 31 case 8: asm("vmovdqa %%ymm8, %0" : "=m"(*data)); break;
> 32 case 9: asm("vmovdqa %%ymm9, %0" : "=m"(*data)); break;
> 33 case 10: asm("vmovdqa %%ymm10, %0" : "=m"(*data)); break;
> 34 case 11: asm("vmovdqa %%ymm11, %0" : "=m"(*data)); break;
> 35 case 12: asm("vmovdqa %%ymm12, %0" : "=m"(*data)); break;
> 36 case 13: asm("vmovdqa %%ymm13, %0" : "=m"(*data)); break;
> 37 case 14: asm("vmovdqa %%ymm14, %0" : "=m"(*data)); break;
> 38 case 15: asm("vmovdqa %%ymm15, %0" : "=m"(*data)); break;
39 default: BUG();
40 }
41 }
42
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Paolo,
kernel test robot noticed the following build errors:
[auto build test ERROR on v6.18-rc5]
[also build test ERROR on linus/master next-20251114]
[cannot apply to kvm/queue kvm/next mst-vhost/linux-next kvm/linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Paolo-Bonzini/KVM-emulate-add-MOVNTDQA/20251114-084216
base: v6.18-rc5
patch link: https://lore.kernel.org/r/20251114003633.60689-8-pbonzini%40redhat.com
patch subject: [PATCH 07/10] KVM: emulate: add AVX support to register fetch and writeback
config: i386-buildonly-randconfig-002-20251114 (https://download.01.org/0day-ci/archive/20251115/202511150016.KszKz14N-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251115/202511150016.KszKz14N-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511150016.KszKz14N-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
>> arch/x86/kvm/fpu.h:60:15: error: register %ymm14 is only available in 64-bit mode
60 | case 14: asm("vmovdqa %0, %%ymm14" : : "m"(*data)); break;
| ^
<inline asm>:1:20: note: instantiated into assembly here
1 | vmovdqa 32(%esi), %ymm14
| ^~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
>> arch/x86/kvm/fpu.h:57:15: error: register %ymm11 is only available in 64-bit mode
57 | case 11: asm("vmovdqa %0, %%ymm11" : : "m"(*data)); break;
| ^
<inline asm>:1:20: note: instantiated into assembly here
1 | vmovdqa 32(%esi), %ymm11
| ^~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
>> arch/x86/kvm/fpu.h:58:15: error: register %ymm12 is only available in 64-bit mode
58 | case 12: asm("vmovdqa %0, %%ymm12" : : "m"(*data)); break;
| ^
<inline asm>:1:20: note: instantiated into assembly here
1 | vmovdqa 32(%esi), %ymm12
| ^~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
>> arch/x86/kvm/fpu.h:55:15: error: register %ymm9 is only available in 64-bit mode
55 | case 9: asm("vmovdqa %0, %%ymm9" : : "m"(*data)); break;
| ^
<inline asm>:1:20: note: instantiated into assembly here
1 | vmovdqa 32(%esi), %ymm9
| ^~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
>> arch/x86/kvm/fpu.h:61:15: error: register %ymm15 is only available in 64-bit mode
61 | case 15: asm("vmovdqa %0, %%ymm15" : : "m"(*data)); break;
| ^
<inline asm>:1:20: note: instantiated into assembly here
1 | vmovdqa 32(%esi), %ymm15
| ^~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
>> arch/x86/kvm/fpu.h:59:15: error: register %ymm13 is only available in 64-bit mode
59 | case 13: asm("vmovdqa %0, %%ymm13" : : "m"(*data)); break;
| ^
<inline asm>:1:20: note: instantiated into assembly here
1 | vmovdqa 32(%esi), %ymm13
| ^~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
>> arch/x86/kvm/fpu.h:56:15: error: register %ymm10 is only available in 64-bit mode
56 | case 10: asm("vmovdqa %0, %%ymm10" : : "m"(*data)); break;
| ^
<inline asm>:1:20: note: instantiated into assembly here
1 | vmovdqa 32(%esi), %ymm10
| ^~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
>> arch/x86/kvm/fpu.h:54:15: error: register %ymm8 is only available in 64-bit mode
54 | case 8: asm("vmovdqa %0, %%ymm8" : : "m"(*data)); break;
| ^
<inline asm>:1:20: note: instantiated into assembly here
1 | vmovdqa 32(%esi), %ymm8
| ^~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
arch/x86/kvm/fpu.h:37:15: error: register %ymm14 is only available in 64-bit mode
37 | case 14: asm("vmovdqa %%ymm14, %0" : "=m"(*data)); break;
| ^
<inline asm>:1:10: note: instantiated into assembly here
1 | vmovdqa %ymm14, 32(%esi)
| ^~~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
arch/x86/kvm/fpu.h:34:15: error: register %ymm11 is only available in 64-bit mode
34 | case 11: asm("vmovdqa %%ymm11, %0" : "=m"(*data)); break;
| ^
<inline asm>:1:10: note: instantiated into assembly here
1 | vmovdqa %ymm11, 32(%esi)
| ^~~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
arch/x86/kvm/fpu.h:35:15: error: register %ymm12 is only available in 64-bit mode
35 | case 12: asm("vmovdqa %%ymm12, %0" : "=m"(*data)); break;
| ^
<inline asm>:1:10: note: instantiated into assembly here
1 | vmovdqa %ymm12, 32(%esi)
| ^~~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
arch/x86/kvm/fpu.h:32:15: error: register %ymm9 is only available in 64-bit mode
32 | case 9: asm("vmovdqa %%ymm9, %0" : "=m"(*data)); break;
| ^
<inline asm>:1:10: note: instantiated into assembly here
1 | vmovdqa %ymm9, 32(%esi)
| ^~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
arch/x86/kvm/fpu.h:38:15: error: register %ymm15 is only available in 64-bit mode
38 | case 15: asm("vmovdqa %%ymm15, %0" : "=m"(*data)); break;
| ^
<inline asm>:1:10: note: instantiated into assembly here
1 | vmovdqa %ymm15, 32(%esi)
| ^~~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
arch/x86/kvm/fpu.h:36:15: error: register %ymm13 is only available in 64-bit mode
36 | case 13: asm("vmovdqa %%ymm13, %0" : "=m"(*data)); break;
| ^
<inline asm>:1:10: note: instantiated into assembly here
1 | vmovdqa %ymm13, 32(%esi)
| ^~~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
arch/x86/kvm/fpu.h:33:15: error: register %ymm10 is only available in 64-bit mode
33 | case 10: asm("vmovdqa %%ymm10, %0" : "=m"(*data)); break;
| ^
<inline asm>:1:10: note: instantiated into assembly here
1 | vmovdqa %ymm10, 32(%esi)
| ^~~~~~~
In file included from arch/x86/kvm/emulate.c:24:
In file included from arch/x86/kvm/kvm_emulate.h:16:
arch/x86/kvm/fpu.h:31:15: error: register %ymm8 is only available in 64-bit mode
31 | case 8: asm("vmovdqa %%ymm8, %0" : "=m"(*data)); break;
| ^
<inline asm>:1:10: note: instantiated into assembly here
1 | vmovdqa %ymm8, 32(%esi)
| ^~~~~~
16 errors generated.
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for I2C_K1
Depends on [n]: I2C [=y] && HAS_IOMEM [=y] && (ARCH_SPACEMIT || COMPILE_TEST [=y]) && OF [=n]
Selected by [m]:
- MFD_SPACEMIT_P1 [=m] && HAS_IOMEM [=y] && (ARCH_SPACEMIT || COMPILE_TEST [=y]) && I2C [=y]
vim +60 arch/x86/kvm/fpu.h
42
43 static inline void _kvm_write_avx_reg(int reg, const avx256_t *data)
44 {
45 switch (reg) {
46 case 0: asm("vmovdqa %0, %%ymm0" : : "m"(*data)); break;
47 case 1: asm("vmovdqa %0, %%ymm1" : : "m"(*data)); break;
48 case 2: asm("vmovdqa %0, %%ymm2" : : "m"(*data)); break;
49 case 3: asm("vmovdqa %0, %%ymm3" : : "m"(*data)); break;
50 case 4: asm("vmovdqa %0, %%ymm4" : : "m"(*data)); break;
51 case 5: asm("vmovdqa %0, %%ymm5" : : "m"(*data)); break;
52 case 6: asm("vmovdqa %0, %%ymm6" : : "m"(*data)); break;
53 case 7: asm("vmovdqa %0, %%ymm7" : : "m"(*data)); break;
> 54 case 8: asm("vmovdqa %0, %%ymm8" : : "m"(*data)); break;
> 55 case 9: asm("vmovdqa %0, %%ymm9" : : "m"(*data)); break;
> 56 case 10: asm("vmovdqa %0, %%ymm10" : : "m"(*data)); break;
> 57 case 11: asm("vmovdqa %0, %%ymm11" : : "m"(*data)); break;
> 58 case 12: asm("vmovdqa %0, %%ymm12" : : "m"(*data)); break;
> 59 case 13: asm("vmovdqa %0, %%ymm13" : : "m"(*data)); break;
> 60 case 14: asm("vmovdqa %0, %%ymm14" : : "m"(*data)); break;
> 61 case 15: asm("vmovdqa %0, %%ymm15" : : "m"(*data)); break;
62 default: BUG();
63 }
64 }
65
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