On Fri Nov 14, 2025 at 6:53 PM CET, Miquel Raynal wrote:
> There are two status registers, named 1 and 2, all the opcodes imply a 1
> byte access. Make it clear by aligning all comments on the same pattern,
> for the four "{read,write} status {1,2} registers" definitions.
Not sure, what you mean. The current comment implies 1 byte access.
But that is wrong because the WRSR can be used to write both the SR1
and SR2 (or sometimes called CR).
With that fixed:
Reviewed-by: Michael Walle <mwalle@kernel.org>
-michael
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> include/linux/mtd/spi-nor.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index cdcfe0fd2e7d624bbb66fefcb87823bce300268e..90a0cf58351295c63baea4f064b49b7390337d37 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -21,8 +21,8 @@
> /* Flash opcodes. */
> #define SPINOR_OP_WRDI 0x04 /* Write disable */
> #define SPINOR_OP_WREN 0x06 /* Write enable */
> -#define SPINOR_OP_RDSR 0x05 /* Read status register */
> -#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
> +#define SPINOR_OP_RDSR 0x05 /* Read status register 1 */
> +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 */
> #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
> #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
> #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */