Currently, only bit 63 is ignored when reading LBR MSRs. However,
different AMD CPUs use upper bits of the MSR differently. For example,
some Zen 4 processors document bit 63 in LASTBRACNHFROMIP and bits 63:61
in LASTBRANCHTOIP to be reserved. On the other hand, some Zen 5
processors bits 63:57 to be reserved in both MSRs.

Use the common denominator and always bits 63:57 when reading the LBR
MSRs, which should be sufficient testing. This fixes the test flaking on
some AMD processors that set bit 62 in LASTBRANCHTOIP.

Reported-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Yosry Ahmed <yosry.ahmed@linux.dev>
---
 lib/x86/msr.h   | 8 ++++++--
 x86/svm_tests.c | 2 +-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/lib/x86/msr.h b/lib/x86/msr.h
index cc4cb8551ea1b..e586a8e931900 100644
--- a/lib/x86/msr.h
+++ b/lib/x86/msr.h
@@ -85,8 +85,12 @@
 #define MSR_IA32_LASTINTFROMIP		0x000001dd
 #define MSR_IA32_LASTINTTOIP		0x000001de
 
-/* Yes, AMD does indeed record mispredict info in the LBR records themselves. */
-#define AMD_LBR_RECORD_MISPREDICT	BIT_ULL(63)
+/*
+ * Different AMD CPUs use the upper bits of the IP LBRs differently. For the
+ * purposes of tests, use the common denominator of the IP bits.
+ */
+#define AMD_LBR_RECORD_IP_BITS		57
+#define AMD_LBR_RECORD_IP_MASK		((1UL << AMD_LBR_RECORD_IP_BITS)-1)
 
 #define LBR_INFO_MISPRED		BIT_ULL(63)
 #define LBR_INFO_IN_TX			BIT_ULL(62)
diff --git a/x86/svm_tests.c b/x86/svm_tests.c
index 80d5aeb108650..43e76badf1638 100644
--- a/x86/svm_tests.c
+++ b/x86/svm_tests.c
@@ -2953,7 +2953,7 @@ static void svm_no_nm_test(void)
 
 static u64 amd_get_lbr_rip(u32 msr)
 {
-	return rdmsr(msr) & ~AMD_LBR_RECORD_MISPREDICT;
+	return rdmsr(msr) & AMD_LBR_RECORD_IP_MASK;
 }
 
 #define HOST_CHECK_LBR(from_expected, to_expected)					\
-- 
2.52.0.rc1.455.g30608eb744-goog

On Thu, 13 Nov 2025 22:46:39 +0000, Yosry Ahmed wrote:
> Currently, only bit 63 is ignored when reading LBR MSRs. However,
> different AMD CPUs use upper bits of the MSR differently. For example,
> some Zen 4 processors document bit 63 in LASTBRACNHFROMIP and bits 63:61
> in LASTBRANCHTOIP to be reserved. On the other hand, some Zen 5
> processors bits 63:57 to be reserved in both MSRs.
> 
> Use the common denominator and always bits 63:57 when reading the LBR
> MSRs, which should be sufficient testing. This fixes the test flaking on
> some AMD processors that set bit 62 in LASTBRANCHTOIP.
> 
> [...]

Applied to kvm-x86 next, thanks!

[1/1] x86/svm: Correctly extract the IP from LBR MSRs
      https://github.com/kvm-x86/kvm-unit-tests/commit/9a7a0e188bd7

--
https://github.com/kvm-x86/kvm-unit-tests/tree/next