Add DT binding schema for Realtek system controller.
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
---
.../devicetree/bindings/mfd/realtek,misc.yaml | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/realtek,misc.yaml
diff --git a/Documentation/devicetree/bindings/mfd/realtek,misc.yaml b/Documentation/devicetree/bindings/mfd/realtek,misc.yaml
new file mode 100644
index 000000000000..4f4a9ae250be
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/realtek,misc.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/realtek,misc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek MISC System Controller
+
+description:
+ The Realtek MISC System Controller is a register area that contains
+ miscellaneous system registers for the SoC and serves as a parent node
+ for other functions.
+
+maintainers:
+ - James Tai <james.tai@realtek.com>
+ - Yu-Chun Lin <eleanor.lin@realtek.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - realtek,misc
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ ranges:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ "^serial@[0-9a-f]+$":
+ type: object
+ description: UART controllers inside MISC area
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ syscon@7000 {
+ compatible = "realtek,misc", "syscon", "simple-mfd";
+ reg = <0x7000 0x1000>;
+ ranges = <0x0 0x7000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x800 0x100>;
+ clock-frequency = <432000000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
--
2.34.1
On 13/11/2025 13:30, Yu-Chun Lin wrote:
> Add DT binding schema for Realtek system controller.
What is Realtek system controller? I already asked.
I have Realtek WiFi RT8192, so it is the same, right?
>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> .../devicetree/bindings/mfd/realtek,misc.yaml | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/realtek,misc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/realtek,misc.yaml b/Documentation/devicetree/bindings/mfd/realtek,misc.yaml
> new file mode 100644
> index 000000000000..4f4a9ae250be
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/realtek,misc.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/realtek,misc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Realtek MISC System Controller
> +
> +description:
> + The Realtek MISC System Controller is a register area that contains
> + miscellaneous system registers for the SoC and serves as a parent node
> + for other functions.
> +
> +maintainers:
> + - James Tai <james.tai@realtek.com>
> + - Yu-Chun Lin <eleanor.lin@realtek.com>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - realtek,misc
Nothing improved, still no soc part. You received comment on that - you
need soc specific compatibles.
Explain properly what is the hardware. You have entire commit msg for that.
Did you read writing bindings doc?
> + - const: syscon
> + - const: simple-mfd
> +
> + reg:
> + maxItems: 1
> +
> + ranges:
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 1
> +
> +patternProperties:
> + "^serial@[0-9a-f]+$":
> + type: object
> + description: UART controllers inside MISC area
Please read what is a syscon. Then please bring justification why you
claim that SNPS block is part of miscellaneous registers, because it
highly unlikely. Reach to your hardware engineers to explain that.
> +
> +required:
> + - compatible
> + - reg
> + - ranges
> + - '#address-cells'
> + - '#size-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + syscon@7000 {
> + compatible = "realtek,misc", "syscon", "simple-mfd";
> + reg = <0x7000 0x1000>;
> + ranges = <0x0 0x7000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + uart0: serial@800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x800 0x100>;
> + clock-frequency = <432000000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
Your code is not improving, but going opposite direction. There is no
such code in the bindings, drop.
> + };
> + };
Best regards,
Krzysztof
On Thu, Nov 13, 2025 at 08:30:08PM +0800, Yu-Chun Lin wrote:
> Add DT binding schema for Realtek system controller.
>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> .../devicetree/bindings/mfd/realtek,misc.yaml | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/realtek,misc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/realtek,misc.yaml b/Documentation/devicetree/bindings/mfd/realtek,misc.yaml
> new file mode 100644
> index 000000000000..4f4a9ae250be
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/realtek,misc.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/realtek,misc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Realtek MISC System Controller
> +
> +description:
> + The Realtek MISC System Controller is a register area that contains
> + miscellaneous system registers for the SoC and serves as a parent node
> + for other functions.
> +
> +maintainers:
> + - James Tai <james.tai@realtek.com>
> + - Yu-Chun Lin <eleanor.lin@realtek.com>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - realtek,misc
You need a soc-specific compatible. It's hard to believe that every
realtek device will have the exact same miscellaneous register region ;)
> + - const: syscon
> + - const: simple-mfd
> +
> + reg:
> + maxItems: 1
> +
> + ranges:
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 1
> +
> +patternProperties:
> + "^serial@[0-9a-f]+$":
> + type: object
> + description: UART controllers inside MISC area
How many of these actually are there?
If they're always dw uarts, please add a reference to that schema.
pw-bot: changes-requested
> +
> +required:
> + - compatible
> + - reg
> + - ranges
> + - '#address-cells'
> + - '#size-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + syscon@7000 {
> + compatible = "realtek,misc", "syscon", "simple-mfd";
> + reg = <0x7000 0x1000>;
> + ranges = <0x0 0x7000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + uart0: serial@800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x800 0x100>;
> + clock-frequency = <432000000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> --
> 2.34.1
>
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