From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Add the devicetree binding for PCIe M.2 Mechanical Key E connector defined
in the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector
provides interfaces like PCIe or SDIO to attach the WiFi devices to the
host machine, USB or UART+PCM interfaces to attach the Bluetooth (BT)
devices along with additional interfaces like I2C for NFC solution. At any
point of time, the connector can only support either PCIe or SDIO as the
WiFi interface and USB or UART as the BT interface.
The connector provides a primary power supply of 3.3v, along with an
optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at
1.8v sideband signaling.
The connector also supplies optional signals in the form of GPIOs for fine
grained power management.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
.../bindings/connector/pcie-m2-e-connector.yaml | 154 +++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 155 insertions(+)
diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..91cb56b1a75b7e3de3b9fe9a7537089f96875746
--- /dev/null
+++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PCIe M.2 Mechanical Key E Connector
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
+
+description:
+ A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E
+ connector. Mechanical Key E connectors are used to connect Wireless
+ Connectivity devices including combinations of Wi-Fi, BT, NFC to the host
+ machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C.
+
+properties:
+ compatible:
+ const: pcie-m2-e-connector
+
+ vpcie3v3-supply:
+ description: A phandle to the regulator for 3.3v supply.
+
+ vpcie1v8-supply:
+ description: A phandle to the regulator for VIO 1.8v supply.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: OF graph bindings modeling the interfaces exposed on the
+ connector. Since a single connector can have multiple interfaces, every
+ interface has an assigned OF graph port number as described below.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: PCIe/SDIO interface
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: USB 2.0/UART interface
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: PCM/I2S interface
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: I2C interface
+
+ oneOf:
+ - required:
+ - port@0
+
+ clocks:
+ description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
+ the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
+ more details.
+ maxItems: 1
+
+ w_disable1-gpios:
+ description: GPIO controlled connection to W_DISABLE1# signal. This signal
+ is used by the system to disable WiFi radio in the M.2 card. Refer, PCI
+ Express M.2 Specification r4.0, sec 3.1.12.3 for more details.
+ maxItems: 1
+
+ w_disable2-gpios:
+ description: GPIO controlled connection to W_DISABLE2# signal. This signal
+ is used by the system to disable BT radio in the M.2 card. Refer, PCI
+ Express M.2 Specification r4.0, sec 3.1.12.3 for more details.
+ maxItems: 1
+
+ led1-gpios:
+ description: GPIO controlled connection to LED_1# signal. This signal is
+ used by the M.2 card to indicate the card status via the system mounted
+ LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more
+ details.
+ maxItems: 1
+
+ led2-gpios:
+ description: GPIO controlled connection to LED_2# signal. This signal is
+ used by the M.2 card to indicate the card status via the system mounted
+ LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more
+ details.
+ maxItems: 1
+
+ viocfg-gpios:
+ description: GPIO controlled connection to IO voltage configuration
+ (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the
+ host system that the card supports an independent IO voltage domain for
+ the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec
+ 3.1.15.1 for more details.
+ maxItems: 1
+
+ uim_power_src-gpios:
+ description: GPIO controlled connection to UIM_POWER_SRC signal. This signal
+ is used when the NFC solution is implemented and receives the power output
+ from WWAN_UIM_PWR signal of the another WWAN M.2 card. Refer, PCI Express
+ M.2 Specification r4.0, sec 3.1.11.1 for more details.
+ maxItems: 1
+
+ uim_power_snk-gpios:
+ description: GPIO controlled connection to UIM_POWER_SNK signal. This signal
+ is used when the NFC solution is implemented and supplies power to the
+ Universal Integrated Circuit Card (UICC). Refer, PCI Express M.2
+ Specification r4.0, sec 3.1.11.2 for more details.
+ maxItems: 1
+
+ uim_swp-gpios:
+ description: GPIO controlled connection to UIM_SWP signal. This signal is
+ used when the NFC solution is implemented and implements the Single Wire
+ Protocol (SWP) interface to the UICC. Refer, PCI Express M.2 Specification
+ r4.0, sec 3.1.11.3 for more details.
+ maxItems: 1
+
+required:
+ - compatible
+ - vpcie3v3-supply
+
+additionalProperties: false
+
+examples:
+ # PCI M.2 Key E connector for WLAN/BT with PCIe/UART interfaces
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ connector {
+ compatible = "pcie-m2-e-connector";
+ vpcie3v3-supply = <&vreg_wcn_3p3>;
+ vpcie1v8-supply = <&vreg_l15b_1p8>;
+ w_disable1-gpios = <&tlmm 117 GPIO_ACTIVE_LOW>;
+ w_disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ endpoint {
+ remote-endpoint = <&pcie4_port0_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ endpoint {
+ remote-endpoint = <&uart14_ep>;
+ };
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 9b3f689d1f50c62afa3772a0c6802f99a98ac2de..f707f29d0a37f344d8dd061b7e49dbb807933c9f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20478,6 +20478,7 @@ PCIE M.2 POWER SEQUENCING
M: Manivannan Sadhasivam <mani@kernel.org>
L: linux-pci@vger.kernel.org
S: Maintained
+F: Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml
F: drivers/power/sequencing/pwrseq-pcie-m2.c
--
2.48.1On Wed, Nov 12, 2025 at 08:15:19PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
>
> Add the devicetree binding for PCIe M.2 Mechanical Key E connector defined
> in the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector
> provides interfaces like PCIe or SDIO to attach the WiFi devices to the
> host machine, USB or UART+PCM interfaces to attach the Bluetooth (BT)
> devices along with additional interfaces like I2C for NFC solution. At any
> point of time, the connector can only support either PCIe or SDIO as the
> WiFi interface and USB or UART as the BT interface.
>
> The connector provides a primary power supply of 3.3v, along with an
> optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at
> 1.8v sideband signaling.
>
> The connector also supplies optional signals in the form of GPIOs for fine
> grained power management.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
> .../bindings/connector/pcie-m2-e-connector.yaml | 154 +++++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 155 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..91cb56b1a75b7e3de3b9fe9a7537089f96875746
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
> @@ -0,0 +1,154 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: PCIe M.2 Mechanical Key E Connector
> +
> +maintainers:
> + - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> +
> +description:
> + A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E
> + connector. Mechanical Key E connectors are used to connect Wireless
> + Connectivity devices including combinations of Wi-Fi, BT, NFC to the host
> + machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C.
> +
> +properties:
> + compatible:
> + const: pcie-m2-e-connector
> +
> + vpcie3v3-supply:
> + description: A phandle to the regulator for 3.3v supply.
> +
> + vpcie1v8-supply:
> + description: A phandle to the regulator for VIO 1.8v supply.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + description: OF graph bindings modeling the interfaces exposed on the
> + connector. Since a single connector can have multiple interfaces, every
> + interface has an assigned OF graph port number as described below.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: PCIe/SDIO interface
The same comment as for the M-key bindings: please describe endpoints.
> + led1-gpios:
> + description: GPIO controlled connection to LED_1# signal. This signal is
> + used by the M.2 card to indicate the card status via the system mounted
> + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more
> + details.
How are we supposed to handle these LEDs? I have been assuming that
these pins should go striaght to the LED driver.
> + maxItems: 1
> +
> + led2-gpios:
> + description: GPIO controlled connection to LED_2# signal. This signal is
> + used by the M.2 card to indicate the card status via the system mounted
> + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more
> + details.
> + maxItems: 1
> +
> + viocfg-gpios:
> + description: GPIO controlled connection to IO voltage configuration
> + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the
> + host system that the card supports an independent IO voltage domain for
> + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec
> + 3.1.15.1 for more details.
> + maxItems: 1
This more looks like viocfg-supply. Looking at this one and several
other pins, it's more like a GPIO controller, providing those pins for
the system, rather than a GPIO consumer.
> +
> + uim_power_src-gpios:
> + description: GPIO controlled connection to UIM_POWER_SRC signal. This signal
> + is used when the NFC solution is implemented and receives the power output
> + from WWAN_UIM_PWR signal of the another WWAN M.2 card. Refer, PCI Express
> + M.2 Specification r4.0, sec 3.1.11.1 for more details.
> + maxItems: 1
> +
> + uim_power_snk-gpios:
> + description: GPIO controlled connection to UIM_POWER_SNK signal. This signal
> + is used when the NFC solution is implemented and supplies power to the
> + Universal Integrated Circuit Card (UICC). Refer, PCI Express M.2
> + Specification r4.0, sec 3.1.11.2 for more details.
> + maxItems: 1
> +
> + uim_swp-gpios:
> + description: GPIO controlled connection to UIM_SWP signal. This signal is
> + used when the NFC solution is implemented and implements the Single Wire
> + Protocol (SWP) interface to the UICC. Refer, PCI Express M.2 Specification
> + r4.0, sec 3.1.11.3 for more details.
> + maxItems: 1
> +
> +required:
> + - compatible
> + - vpcie3v3-supply
> +
> +additionalProperties: false
> +
> +examples:
> + # PCI M.2 Key E connector for WLAN/BT with PCIe/UART interfaces
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> +
> + connector {
> + compatible = "pcie-m2-e-connector";
> + vpcie3v3-supply = <&vreg_wcn_3p3>;
> + vpcie1v8-supply = <&vreg_l15b_1p8>;
> + w_disable1-gpios = <&tlmm 117 GPIO_ACTIVE_LOW>;
> + w_disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + endpoint {
> + remote-endpoint = <&pcie4_port0_ep>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> +
> + endpoint {
> + remote-endpoint = <&uart14_ep>;
> + };
> + };
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9b3f689d1f50c62afa3772a0c6802f99a98ac2de..f707f29d0a37f344d8dd061b7e49dbb807933c9f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20478,6 +20478,7 @@ PCIE M.2 POWER SEQUENCING
> M: Manivannan Sadhasivam <mani@kernel.org>
> L: linux-pci@vger.kernel.org
> S: Maintained
> +F: Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
> F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml
> F: drivers/power/sequencing/pwrseq-pcie-m2.c
>
>
> --
> 2.48.1
>
>
--
With best wishes
Dmitry
On Wed, Nov 12, 2025 at 10:08:57PM +0200, Dmitry Baryshkov wrote: > On Wed, Nov 12, 2025 at 08:15:19PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > > From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > > > > Add the devicetree binding for PCIe M.2 Mechanical Key E connector defined > > in the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector > > provides interfaces like PCIe or SDIO to attach the WiFi devices to the > > host machine, USB or UART+PCM interfaces to attach the Bluetooth (BT) > > devices along with additional interfaces like I2C for NFC solution. At any > > point of time, the connector can only support either PCIe or SDIO as the > > WiFi interface and USB or UART as the BT interface. > > > > The connector provides a primary power supply of 3.3v, along with an > > optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at > > 1.8v sideband signaling. > > > > The connector also supplies optional signals in the form of GPIOs for fine > > grained power management. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > > --- > > .../bindings/connector/pcie-m2-e-connector.yaml | 154 +++++++++++++++++++++ > > MAINTAINERS | 1 + > > 2 files changed, 155 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..91cb56b1a75b7e3de3b9fe9a7537089f96875746 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml > > @@ -0,0 +1,154 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: PCIe M.2 Mechanical Key E Connector > > + > > +maintainers: > > + - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > > + > > +description: > > + A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E > > + connector. Mechanical Key E connectors are used to connect Wireless > > + Connectivity devices including combinations of Wi-Fi, BT, NFC to the host > > + machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C. > > + > > +properties: > > + compatible: > > + const: pcie-m2-e-connector > > + > > + vpcie3v3-supply: > > + description: A phandle to the regulator for 3.3v supply. > > + > > + vpcie1v8-supply: > > + description: A phandle to the regulator for VIO 1.8v supply. > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + description: OF graph bindings modeling the interfaces exposed on the > > + connector. Since a single connector can have multiple interfaces, every > > + interface has an assigned OF graph port number as described below. > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: PCIe/SDIO interface > > The same comment as for the M-key bindings: please describe endpoints. > Sure. > > + led1-gpios: > > + description: GPIO controlled connection to LED_1# signal. This signal is > > + used by the M.2 card to indicate the card status via the system mounted > > + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more > > + details. > > How are we supposed to handle these LEDs? I have been assuming that > these pins should go striaght to the LED driver. > Yes. I should just drop these. > > + maxItems: 1 > > + > > + led2-gpios: > > + description: GPIO controlled connection to LED_2# signal. This signal is > > + used by the M.2 card to indicate the card status via the system mounted > > + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more > > + details. > > + maxItems: 1 > > + > > + viocfg-gpios: > > + description: GPIO controlled connection to IO voltage configuration > > + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the > > + host system that the card supports an independent IO voltage domain for > > + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec > > + 3.1.15.1 for more details. > > + maxItems: 1 > > This more looks like viocfg-supply. Looking at this one and several > other pins, it's more like a GPIO controller, providing those pins for > the system, rather than a GPIO consumer. > It is not a supply, but rather an indicator to the host. If it is low, then it indicates that the card supports 3.3V on the sideband IO signals. - Mani -- மணிவண்ணன் சதாசிவம்
On Wed, Nov 12, 2025 at 08:15:19PM +0530, Manivannan Sadhasivam wrote:
> Add the devicetree binding for PCIe M.2 Mechanical Key E connector defined
> in the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector
> provides interfaces like PCIe or SDIO to attach the WiFi devices to the
> host machine, USB or UART+PCM interfaces to attach the Bluetooth (BT)
> devices along with additional interfaces like I2C for NFC solution. At any
> point of time, the connector can only support either PCIe or SDIO as the
> WiFi interface and USB or UART as the BT interface.
>
> The connector provides a primary power supply of 3.3v, along with an
> optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at
> 1.8v sideband signaling.
>
> The connector also supplies optional signals in the form of GPIOs for fine
> grained power management.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
> .../bindings/connector/pcie-m2-e-connector.yaml | 154 +++++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 155 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..91cb56b1a75b7e3de3b9fe9a7537089f96875746
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
> @@ -0,0 +1,154 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: PCIe M.2 Mechanical Key E Connector
> +
> +maintainers:
> + - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> +
> +description:
> + A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E
> + connector. Mechanical Key E connectors are used to connect Wireless
> + Connectivity devices including combinations of Wi-Fi, BT, NFC to the host
> + machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C.
> +
> +properties:
> + compatible:
> + const: pcie-m2-e-connector
> +
> + vpcie3v3-supply:
> + description: A phandle to the regulator for 3.3v supply.
> +
> + vpcie1v8-supply:
> + description: A phandle to the regulator for VIO 1.8v supply.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + description: OF graph bindings modeling the interfaces exposed on the
> + connector. Since a single connector can have multiple interfaces, every
> + interface has an assigned OF graph port number as described below.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: PCIe/SDIO interface
PCIe and SDIO is difference signal at key E. why combine to one port? The
similar case is USB2.0/UART
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: USB 2.0/UART interface
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: PCM/I2S interface
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: I2C interface
> +
> + oneOf:
> + - required:
> + - port@0
> +
> + clocks:
> + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
> + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
> + more details.
> + maxItems: 1
Do we need add pciref clock here?
> +
> + w_disable1-gpios:
use "-"
w-disable1-gpios
> + description: GPIO controlled connection to W_DISABLE1# signal. This signal
> + is used by the system to disable WiFi radio in the M.2 card. Refer, PCI
> + Express M.2 Specification r4.0, sec 3.1.12.3 for more details.
> + maxItems: 1
> +
> + w_disable2-gpios:
> + description: GPIO controlled connection to W_DISABLE2# signal. This signal
> + is used by the system to disable BT radio in the M.2 card. Refer, PCI
> + Express M.2 Specification r4.0, sec 3.1.12.3 for more details.
> + maxItems: 1
> +
> + led1-gpios:
> + description: GPIO controlled connection to LED_1# signal. This signal is
> + used by the M.2 card to indicate the card status via the system mounted
> + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more
> + details.
> + maxItems: 1
> +
> + led2-gpios:
> + description: GPIO controlled connection to LED_2# signal. This signal is
> + used by the M.2 card to indicate the card status via the system mounted
> + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more
> + details.
> + maxItems: 1
> +
> + viocfg-gpios:
> + description: GPIO controlled connection to IO voltage configuration
> + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the
> + host system that the card supports an independent IO voltage domain for
> + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec
> + 3.1.15.1 for more details.
> + maxItems: 1
> +
> + uim_power_src-gpios:
property use -
Frank
> + description: GPIO controlled connection to UIM_POWER_SRC signal. This signal
> + is used when the NFC solution is implemented and receives the power output
> + from WWAN_UIM_PWR signal of the another WWAN M.2 card. Refer, PCI Express
> + M.2 Specification r4.0, sec 3.1.11.1 for more details.
> + maxItems: 1
> +
> + uim_power_snk-gpios:
> + description: GPIO controlled connection to UIM_POWER_SNK signal. This signal
> + is used when the NFC solution is implemented and supplies power to the
> + Universal Integrated Circuit Card (UICC). Refer, PCI Express M.2
> + Specification r4.0, sec 3.1.11.2 for more details.
> + maxItems: 1
> +
> + uim_swp-gpios:
> + description: GPIO controlled connection to UIM_SWP signal. This signal is
> + used when the NFC solution is implemented and implements the Single Wire
> + Protocol (SWP) interface to the UICC. Refer, PCI Express M.2 Specification
> + r4.0, sec 3.1.11.3 for more details.
> + maxItems: i1
> +
> +required:
> + - compatible
> + - vpcie3v3-supply
> +
> +additionalProperties: false
> +
> +examples:
> + # PCI M.2 Key E connector for WLAN/BT with PCIe/UART interfaces
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> +
> + connector {
> + compatible = "pcie-m2-e-connector";
> + vpcie3v3-supply = <&vreg_wcn_3p3>;
> + vpcie1v8-supply = <&vreg_l15b_1p8>;
> + w_disable1-gpios = <&tlmm 117 GPIO_ACTIVE_LOW>;
> + w_disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + endpoint {
> + remote-endpoint = <&pcie4_port0_ep>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> +
> + endpoint {
> + remote-endpoint = <&uart14_ep>;
> + };
> + };
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9b3f689d1f50c62afa3772a0c6802f99a98ac2de..f707f29d0a37f344d8dd061b7e49dbb807933c9f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20478,6 +20478,7 @@ PCIE M.2 POWER SEQUENCING
> M: Manivannan Sadhasivam <mani@kernel.org>
> L: linux-pci@vger.kernel.org
> S: Maintained
> +F: Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
> F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml
> F: drivers/power/sequencing/pwrseq-pcie-m2.c
>
>
> --
> 2.48.1
>
On Wed, Nov 12, 2025 at 12:11:56PM -0500, Frank Li wrote: > On Wed, Nov 12, 2025 at 08:15:19PM +0530, Manivannan Sadhasivam wrote: > > Add the devicetree binding for PCIe M.2 Mechanical Key E connector defined > > in the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector > > provides interfaces like PCIe or SDIO to attach the WiFi devices to the > > host machine, USB or UART+PCM interfaces to attach the Bluetooth (BT) > > devices along with additional interfaces like I2C for NFC solution. At any > > point of time, the connector can only support either PCIe or SDIO as the > > WiFi interface and USB or UART as the BT interface. > > > > The connector provides a primary power supply of 3.3v, along with an > > optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at > > 1.8v sideband signaling. > > > > The connector also supplies optional signals in the form of GPIOs for fine > > grained power management. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > > --- > > .../bindings/connector/pcie-m2-e-connector.yaml | 154 +++++++++++++++++++++ > > MAINTAINERS | 1 + > > 2 files changed, 155 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..91cb56b1a75b7e3de3b9fe9a7537089f96875746 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml > > @@ -0,0 +1,154 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: PCIe M.2 Mechanical Key E Connector > > + > > +maintainers: > > + - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > > + > > +description: > > + A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E > > + connector. Mechanical Key E connectors are used to connect Wireless > > + Connectivity devices including combinations of Wi-Fi, BT, NFC to the host > > + machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C. > > + > > +properties: > > + compatible: > > + const: pcie-m2-e-connector > > + > > + vpcie3v3-supply: > > + description: A phandle to the regulator for 3.3v supply. > > + > > + vpcie1v8-supply: > > + description: A phandle to the regulator for VIO 1.8v supply. > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + description: OF graph bindings modeling the interfaces exposed on the > > + connector. Since a single connector can have multiple interfaces, every > > + interface has an assigned OF graph port number as described below. > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: PCIe/SDIO interface > > > PCIe and SDIO is difference signal at key E. why combine to one port? The > similar case is USB2.0/UART > They will be defined as separate endpoints in the next version. > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: USB 2.0/UART interface > > + > > + port@2: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: PCM/I2S interface > > + > > + port@3: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: I2C interface > > + > > + oneOf: > > + - required: > > + - port@0 > > + > > + clocks: > > + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to > > + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for > > + more details. > > + maxItems: 1 > > Do we need add pciref clock here? > > > + > > + w_disable1-gpios: > > use "-" > > w-disable1-gpios > I just went with the spec that defines the signal as W_DISABLE. > > + description: GPIO controlled connection to W_DISABLE1# signal. This signal > > + is used by the system to disable WiFi radio in the M.2 card. Refer, PCI > > + Express M.2 Specification r4.0, sec 3.1.12.3 for more details. > > + maxItems: 1 > > + > > + w_disable2-gpios: > > + description: GPIO controlled connection to W_DISABLE2# signal. This signal > > + is used by the system to disable BT radio in the M.2 card. Refer, PCI > > + Express M.2 Specification r4.0, sec 3.1.12.3 for more details. > > + maxItems: 1 > > + > > + led1-gpios: > > + description: GPIO controlled connection to LED_1# signal. This signal is > > + used by the M.2 card to indicate the card status via the system mounted > > + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more > > + details. > > + maxItems: 1 > > + > > + led2-gpios: > > + description: GPIO controlled connection to LED_2# signal. This signal is > > + used by the M.2 card to indicate the card status via the system mounted > > + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more > > + details. > > + maxItems: 1 > > + > > + viocfg-gpios: > > + description: GPIO controlled connection to IO voltage configuration > > + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the > > + host system that the card supports an independent IO voltage domain for > > + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec > > + 3.1.15.1 for more details. > > + maxItems: 1 > > + > > + uim_power_src-gpios: > > property use - > Again, this is as per the spec. If DT maintainers object to it, I'll change it. - Mani -- மணிவண்ணன் சதாசிவம்
On Thu, Nov 13, 2025 at 10:30:42AM +0530, Manivannan Sadhasivam wrote: > On Wed, Nov 12, 2025 at 12:11:56PM -0500, Frank Li wrote: > > On Wed, Nov 12, 2025 at 08:15:19PM +0530, Manivannan Sadhasivam wrote: > > > Add the devicetree binding for PCIe M.2 Mechanical Key E connector defined > > > in the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector > > > provides interfaces like PCIe or SDIO to attach the WiFi devices to the > > > host machine, USB or UART+PCM interfaces to attach the Bluetooth (BT) > > > devices along with additional interfaces like I2C for NFC solution. At any > > > point of time, the connector can only support either PCIe or SDIO as the > > > WiFi interface and USB or UART as the BT interface. > > > > > > The connector provides a primary power supply of 3.3v, along with an > > > optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at > > > 1.8v sideband signaling. > > > > > > The connector also supplies optional signals in the form of GPIOs for fine > > > grained power management. > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > > > --- > > > .../bindings/connector/pcie-m2-e-connector.yaml | 154 +++++++++++++++++++++ > > > MAINTAINERS | 1 + > > > 2 files changed, 155 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml > > > new file mode 100644 > > > index 0000000000000000000000000000000000000000..91cb56b1a75b7e3de3b9fe9a7537089f96875746 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml > > > @@ -0,0 +1,154 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: PCIe M.2 Mechanical Key E Connector > > > + > > > +maintainers: > > > + - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > > > + > > > +description: > > > + A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E > > > + connector. Mechanical Key E connectors are used to connect Wireless > > > + Connectivity devices including combinations of Wi-Fi, BT, NFC to the host > > > + machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C. > > > + > > > +properties: > > > + compatible: > > > + const: pcie-m2-e-connector > > > + > > > + vpcie3v3-supply: > > > + description: A phandle to the regulator for 3.3v supply. > > > + > > > + vpcie1v8-supply: > > > + description: A phandle to the regulator for VIO 1.8v supply. > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + description: OF graph bindings modeling the interfaces exposed on the > > > + connector. Since a single connector can have multiple interfaces, every > > > + interface has an assigned OF graph port number as described below. > > > + > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: PCIe/SDIO interface > > > > > > PCIe and SDIO is difference signal at key E. why combine to one port? The > > similar case is USB2.0/UART > > > > They will be defined as separate endpoints in the next version. > > > > + > > > + port@1: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: USB 2.0/UART interface > > > + > > > + port@2: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: PCM/I2S interface > > > + > > > + port@3: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: I2C interface > > > + > > > + oneOf: > > > + - required: > > > + - port@0 > > > + > > > + clocks: > > > + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to > > > + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for > > > + more details. > > > + maxItems: 1 > > > > Do we need add pciref clock here? > > > > > + > > > + w_disable1-gpios: > > > > use "-" > > > > w-disable1-gpios > > > > I just went with the spec that defines the signal as W_DISABLE. > > > > + description: GPIO controlled connection to W_DISABLE1# signal. This signal > > > + is used by the system to disable WiFi radio in the M.2 card. Refer, PCI > > > + Express M.2 Specification r4.0, sec 3.1.12.3 for more details. > > > + maxItems: 1 > > > + > > > + w_disable2-gpios: > > > + description: GPIO controlled connection to W_DISABLE2# signal. This signal > > > + is used by the system to disable BT radio in the M.2 card. Refer, PCI > > > + Express M.2 Specification r4.0, sec 3.1.12.3 for more details. > > > + maxItems: 1 > > > + > > > + led1-gpios: > > > + description: GPIO controlled connection to LED_1# signal. This signal is > > > + used by the M.2 card to indicate the card status via the system mounted > > > + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more > > > + details. > > > + maxItems: 1 > > > + > > > + led2-gpios: > > > + description: GPIO controlled connection to LED_2# signal. This signal is > > > + used by the M.2 card to indicate the card status via the system mounted > > > + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more > > > + details. > > > + maxItems: 1 > > > + > > > + viocfg-gpios: > > > + description: GPIO controlled connection to IO voltage configuration > > > + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the > > > + host system that the card supports an independent IO voltage domain for > > > + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec > > > + 3.1.15.1 for more details. > > > + maxItems: 1 > > > + > > > + uim_power_src-gpios: > > > > property use - > > > > Again, this is as per the spec. If DT maintainers object to it, I'll change it. Use '-'. Rob
On Wed, Nov 19, 2025 at 05:59:05PM -0600, Rob Herring wrote: > On Thu, Nov 13, 2025 at 10:30:42AM +0530, Manivannan Sadhasivam wrote: > > On Wed, Nov 12, 2025 at 12:11:56PM -0500, Frank Li wrote: > > > On Wed, Nov 12, 2025 at 08:15:19PM +0530, Manivannan Sadhasivam wrote: > > > > Add the devicetree binding for PCIe M.2 Mechanical Key E connector defined > > > > in the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector > > > > provides interfaces like PCIe or SDIO to attach the WiFi devices to the > > > > host machine, USB or UART+PCM interfaces to attach the Bluetooth (BT) > > > > devices along with additional interfaces like I2C for NFC solution. At any > > > > point of time, the connector can only support either PCIe or SDIO as the > > > > WiFi interface and USB or UART as the BT interface. > > > > > > > > The connector provides a primary power supply of 3.3v, along with an > > > > optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at > > > > 1.8v sideband signaling. > > > > > > > > The connector also supplies optional signals in the form of GPIOs for fine > > > > grained power management. > > > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > > > > --- > > > > .../bindings/connector/pcie-m2-e-connector.yaml | 154 +++++++++++++++++++++ > > > > MAINTAINERS | 1 + > > > > 2 files changed, 155 insertions(+) > > > > > > > > diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml > > > > new file mode 100644 > > > > index 0000000000000000000000000000000000000000..91cb56b1a75b7e3de3b9fe9a7537089f96875746 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml > > > > @@ -0,0 +1,154 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: PCIe M.2 Mechanical Key E Connector > > > > + > > > > +maintainers: > > > > + - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > > > > + > > > > +description: > > > > + A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E > > > > + connector. Mechanical Key E connectors are used to connect Wireless > > > > + Connectivity devices including combinations of Wi-Fi, BT, NFC to the host > > > > + machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C. > > > > + > > > > +properties: > > > > + compatible: > > > > + const: pcie-m2-e-connector > > > > + > > > > + vpcie3v3-supply: > > > > + description: A phandle to the regulator for 3.3v supply. > > > > + > > > > + vpcie1v8-supply: > > > > + description: A phandle to the regulator for VIO 1.8v supply. > > > > + > > > > + ports: > > > > + $ref: /schemas/graph.yaml#/properties/ports > > > > + description: OF graph bindings modeling the interfaces exposed on the > > > > + connector. Since a single connector can have multiple interfaces, every > > > > + interface has an assigned OF graph port number as described below. > > > > + > > > > + properties: > > > > + port@0: > > > > + $ref: /schemas/graph.yaml#/properties/port > > > > + description: PCIe/SDIO interface > > > > > > > > > PCIe and SDIO is difference signal at key E. why combine to one port? The > > > similar case is USB2.0/UART > > > > > > > They will be defined as separate endpoints in the next version. > > > > > > + > > > > + port@1: > > > > + $ref: /schemas/graph.yaml#/properties/port > > > > + description: USB 2.0/UART interface > > > > + > > > > + port@2: > > > > + $ref: /schemas/graph.yaml#/properties/port > > > > + description: PCM/I2S interface > > > > + > > > > + port@3: > > > > + $ref: /schemas/graph.yaml#/properties/port > > > > + description: I2C interface > > > > + > > > > + oneOf: > > > > + - required: > > > > + - port@0 > > > > + > > > > + clocks: > > > > + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to > > > > + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for > > > > + more details. > > > > + maxItems: 1 > > > > > > Do we need add pciref clock here? > > > > > > > + > > > > + w_disable1-gpios: > > > > > > use "-" > > > > > > w-disable1-gpios > > > > > > > I just went with the spec that defines the signal as W_DISABLE. > > > > > > + description: GPIO controlled connection to W_DISABLE1# signal. This signal > > > > + is used by the system to disable WiFi radio in the M.2 card. Refer, PCI > > > > + Express M.2 Specification r4.0, sec 3.1.12.3 for more details. > > > > + maxItems: 1 > > > > + > > > > + w_disable2-gpios: > > > > + description: GPIO controlled connection to W_DISABLE2# signal. This signal > > > > + is used by the system to disable BT radio in the M.2 card. Refer, PCI > > > > + Express M.2 Specification r4.0, sec 3.1.12.3 for more details. > > > > + maxItems: 1 > > > > + > > > > + led1-gpios: > > > > + description: GPIO controlled connection to LED_1# signal. This signal is > > > > + used by the M.2 card to indicate the card status via the system mounted > > > > + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more > > > > + details. > > > > + maxItems: 1 > > > > + > > > > + led2-gpios: > > > > + description: GPIO controlled connection to LED_2# signal. This signal is > > > > + used by the M.2 card to indicate the card status via the system mounted > > > > + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more > > > > + details. > > > > + maxItems: 1 > > > > + > > > > + viocfg-gpios: > > > > + description: GPIO controlled connection to IO voltage configuration > > > > + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the > > > > + host system that the card supports an independent IO voltage domain for > > > > + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec > > > > + 3.1.15.1 for more details. > > > > + maxItems: 1 > > > > + > > > > + uim_power_src-gpios: > > > > > > property use - > > > > > > > Again, this is as per the spec. If DT maintainers object to it, I'll change it. > > Use '-'. > OK! - Mani -- மணிவண்ணன் சதாசிவம்
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