On the Renesas RZ/V2H EVK platform, where the stmmac MAC is connected to a
Microchip KSZ9131RNXI PHY, creating or deleting VLAN interfaces may fail
with timeouts:

    # ip link add link end1 name end1.5 type vlan id 5
    15c40000.ethernet end1: Timeout accessing MAC_VLAN_Tag_Filter
    RTNETLINK answers: Device or resource busy

Disabling EEE at runtime avoids the problem:

    # ethtool --set-eee end1 eee off
    # ip link add link end1 name end1.5 type vlan id 5
    # ip link del end1.5

The stmmac hardware requires the receive clock to be running when writing
certain registers, such as those used for MAC address configuration or
VLAN filtering. However, by default the driver enables Energy Efficient
Ethernet (EEE) and allows the PHY to stop the receive clock when the link
is idle. As a result, the RX clock might be stopped when attempting to
access these registers, leading to timeouts and other issues.

Commit dd557266cf5fb ("net: stmmac: block PHY RXC clock-stop")
addressed this issue for most register accesses by wrapping them in
phylink_rx_clk_stop_block()/phylink_rx_clk_stop_unblock() calls.
However, VLAN add/delete operations may be invoked with bottom halves
disabled, where sleeping is not allowed, so using these helpers is not
possible.

Therefore, to fix this, disable the RX clock stop feature in the phylink
configuration if VLAN features are set. This ensures the RX clock remains
active and register accesses succeed during VLAN operations.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index ba4eeba14baa..0d3fb4fa5e12 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1245,7 +1245,8 @@ static int stmmac_phylink_setup(struct stmmac_priv *priv)
 	/* Stmmac always requires an RX clock for hardware initialization */
 	config->mac_requires_rxc = true;
 
-	if (!(priv->plat->flags & STMMAC_FLAG_RX_CLK_RUNS_IN_LPI))
+	if (!(priv->plat->flags & STMMAC_FLAG_RX_CLK_RUNS_IN_LPI) &&
+	    !(priv->dev->features & NETIF_F_VLAN_FEATURES))
 		config->eee_rx_clk_stop_enable = true;
 
 	/* Set the default transmit clock stop bit based on the platform glue */
-- 
2.51.0

On Tue, Nov 11, 2025 at 09:30:00AM +0000, Ovidiu Panait wrote:
> On the Renesas RZ/V2H EVK platform, where the stmmac MAC is connected to a
> Microchip KSZ9131RNXI PHY, creating or deleting VLAN interfaces may fail
> with timeouts:
> 
>     # ip link add link end1 name end1.5 type vlan id 5
>     15c40000.ethernet end1: Timeout accessing MAC_VLAN_Tag_Filter
>     RTNETLINK answers: Device or resource busy
> 
> Disabling EEE at runtime avoids the problem:
> 
>     # ethtool --set-eee end1 eee off
>     # ip link add link end1 name end1.5 type vlan id 5
>     # ip link del end1.5
> 
> The stmmac hardware requires the receive clock to be running when writing
> certain registers, such as those used for MAC address configuration or
> VLAN filtering. However, by default the driver enables Energy Efficient
> Ethernet (EEE) and allows the PHY to stop the receive clock when the link
> is idle. As a result, the RX clock might be stopped when attempting to
> access these registers, leading to timeouts and other issues.
> 
> Commit dd557266cf5fb ("net: stmmac: block PHY RXC clock-stop")
> addressed this issue for most register accesses by wrapping them in
> phylink_rx_clk_stop_block()/phylink_rx_clk_stop_unblock() calls.
> However, VLAN add/delete operations may be invoked with bottom halves
> disabled, where sleeping is not allowed, so using these helpers is not
> possible.
> 
> Therefore, to fix this, disable the RX clock stop feature in the phylink
> configuration if VLAN features are set. This ensures the RX clock remains
> active and register accesses succeed during VLAN operations.
> 
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>

Thanks for the patch. I guess there is no other way around this, since
as I've previously noted (and as you say above) we can't sleep in the
VLAN ops to access the PHY.

I would like a comment in the code above this if() to state that EEE
RX clock stop is disabled to allow access to VLAN registers to work.
With that added, please add:

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Thanks!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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