arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1 on monaco-evk

[PATCH] arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1 on monaco-evk

Posted by Sushrut Shree Trivedi 2 months, 4 weeks ago

Enables PCIe0 and PCIe1 controller and phy-nodes.

PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
attaches while PCIe1 routes to a standard PCIe x4 expansion slot.

Signed-off-by: Sushrut Shree Trivedi <quic_sushruts@quicinc.com>
---
This patch depends on the series:
https://lore.kernel.org/all/20251024095609.48096-1-ziyue.zhang@oss.qualcomm.com/
---
 arch/arm64/boot/dts/qcom/monaco-evk.dts | 84 +++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index e72cf6725a52..70739f71dd5c 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -408,6 +408,44 @@ &qupv3_id_1 {
 	status = "okay";
 };
 
+&pcie0 {
+	pinctrl-0 = <&pcie0_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcieport0 {
+	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l6a>;
+	vdda-pll-supply = <&vreg_l5a>;
+
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-0 = <&pcie1_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcieport1 {
+	reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_phy {
+	vdda-phy-supply = <&vreg_l6a>;
+	vdda-pll-supply = <&vreg_l5a>;
+
+	status = "okay";
+};
+
 &remoteproc_adsp {
 	firmware-name = "qcom/qcs8300/adsp.mbn";
 
@@ -449,6 +487,52 @@ ethernet0_mdio: ethernet0-mdio-pins {
 		};
 	};
 
+	pcie0_default_state: pcie0-default-state {
+		wake-pins {
+			pins = "gpio0";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		clkreq-pins {
+			pins = "gpio1";
+			function = "pcie0_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-pins {
+			pins = "gpio2";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
+	pcie1_default_state: pcie1-default-state {
+		wake-pins {
+			pins = "gpio21";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		clkreq-pins {
+			pins = "gpio22";
+			function = "pcie1_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-pins {
+			pins = "gpio23";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
 	qup_i2c1_default: qup-i2c1-state {
 		pins = "gpio19", "gpio20";
 		function = "qup0_se1";

---
base-commit: b89214826b1ab0e527303464d6c90e53d290c4f1
change-id: 20251110-monaco-evk-pci-85c9459ce9a2

Best regards,
-- 
Sushrut Shree Trivedi <quic_sushruts@quicinc.com>

Re: [PATCH] arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1 on monaco-evk

Posted by Konrad Dybcio 2 months, 4 weeks ago

On 11/11/25 11:08 AM, Sushrut Shree Trivedi wrote:
> Enables PCIe0 and PCIe1 controller and phy-nodes.
> 
> PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
> attaches while PCIe1 routes to a standard PCIe x4 expansion slot.
> 
> Signed-off-by: Sushrut Shree Trivedi <quic_sushruts@quicinc.com>
> ---
> This patch depends on the series:
> https://lore.kernel.org/all/20251024095609.48096-1-ziyue.zhang@oss.qualcomm.com/
> ---

[...]

> +		perst-pins {
> +			pins = "gpio2";
> +			function = "gpio";
> +			drive-strength = <2>;
> +			bias-pull-down;
> +		};

Neither of the two active-low reset pins should be pull-down, use
bias-disable to avoid spurious assertions

Konrad

Re: [PATCH] arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1 on monaco-evk

Posted by Bjorn Andersson 2 months, 4 weeks ago

On Tue, Nov 11, 2025 at 03:38:16PM +0530, Sushrut Shree Trivedi wrote:

You don't need the "on monaco-evk"-suffix in $subject, because you
already have the (correct) subject prefix.

> Enables PCIe0 and PCIe1 controller and phy-nodes.
> 
> PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
> attaches while PCIe1 routes to a standard PCIe x4 expansion slot.

Flip these two paragraphs, so that you first have the "problem
description" and then the "solution".

> 
> Signed-off-by: Sushrut Shree Trivedi <quic_sushruts@quicinc.com>

Please move to @oss.qualcomm.com if you can.

> ---
> This patch depends on the series:
> https://lore.kernel.org/all/20251024095609.48096-1-ziyue.zhang@oss.qualcomm.com/

There's a request for change on patch 5, so I expect that to be
resubmitted. Please send this patch together with that one, so that I
don't have to solve your dependency problems.

> ---
>  arch/arm64/boot/dts/qcom/monaco-evk.dts | 84 +++++++++++++++++++++++++++++++++
>  1 file changed, 84 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
> index e72cf6725a52..70739f71dd5c 100644
> --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
> @@ -408,6 +408,44 @@ &qupv3_id_1 {
>  	status = "okay";
>  };
>  
> +&pcie0 {

"pcie0" < "qup3_id_1" 

> +	pinctrl-0 = <&pcie0_default_state>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&pcieport0 {
> +	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&pcie0_phy {

"pcie0_phy" < "pcieport0"

> +	vdda-phy-supply = <&vreg_l6a>;
> +	vdda-pll-supply = <&vreg_l5a>;
> +
> +	status = "okay";
> +};
> +
> +&pcie1 {

"pcie1" < "pcieport0"

Please sort these alphanumerically.

> +	pinctrl-0 = <&pcie1_default_state>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&pcieport1 {
> +	reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&pcie1_phy {
> +	vdda-phy-supply = <&vreg_l6a>;
> +	vdda-pll-supply = <&vreg_l5a>;
> +
> +	status = "okay";
> +};
> +
>  &remoteproc_adsp {
>  	firmware-name = "qcom/qcs8300/adsp.mbn";
>  
> @@ -449,6 +487,52 @@ ethernet0_mdio: ethernet0-mdio-pins {
>  		};
>  	};
>  
> +	pcie0_default_state: pcie0-default-state {

And please keep the pinctrl state nodes sorted on first "gpioNN".

Regards,
Bjorn

> +		wake-pins {
> +			pins = "gpio0";
> +			function = "gpio";
> +			drive-strength = <2>;
> +			bias-pull-up;
> +		};
> +
> +		clkreq-pins {
> +			pins = "gpio1";
> +			function = "pcie0_clkreq";
> +			drive-strength = <2>;
> +			bias-pull-up;
> +		};
> +
> +		perst-pins {
> +			pins = "gpio2";
> +			function = "gpio";
> +			drive-strength = <2>;
> +			bias-pull-down;
> +		};
> +	};
> +
> +	pcie1_default_state: pcie1-default-state {
> +		wake-pins {
> +			pins = "gpio21";
> +			function = "gpio";
> +			drive-strength = <2>;
> +			bias-pull-up;
> +		};
> +
> +		clkreq-pins {
> +			pins = "gpio22";
> +			function = "pcie1_clkreq";
> +			drive-strength = <2>;
> +			bias-pull-up;
> +		};
> +
> +		perst-pins {
> +			pins = "gpio23";
> +			function = "gpio";
> +			drive-strength = <2>;
> +			bias-pull-down;
> +		};
> +	};
> +
>  	qup_i2c1_default: qup-i2c1-state {
>  		pins = "gpio19", "gpio20";
>  		function = "qup0_se1";
> 
> ---
> base-commit: b89214826b1ab0e527303464d6c90e53d290c4f1
> change-id: 20251110-monaco-evk-pci-85c9459ce9a2
> 
> Best regards,
> -- 
> Sushrut Shree Trivedi <quic_sushruts@quicinc.com>
>