From: Louis Chauvet <louis.chauvet@bootlin.com>

The dt-bindings for the display, specifically ti,am65x-dss, need to
include a clock property for data edge synchronization. The current
implementation does not correctly apply the data edge sampling property.

To address this, synchronization of writes to two different registers is
required: one in the TIDSS IP (which is already described in the tidss
node) and one is in the Memory Mapped Control Register Modules.

As the Memory Mapped Control Register Modules is located in a different
IP, we need to use a phandle to write values in its registers.

Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")
Cc: stable@vger.kernel.org
Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
Signed-off-by: Swamil Jain <s-jain1@ti.com>
---
 .../devicetree/bindings/display/ti/ti,am65x-dss.yaml        | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
index 361e9cae6896..b9a373b56917 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
+++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
@@ -133,6 +133,12 @@ properties:
       and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
       interface to work.
 
+  ti,clk-ctrl:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      phandle to syscon device node mapping CFG0_CLK_CTRL registers.
+      This property is needed for proper data sampling edge.
+
   max-memory-bandwidth:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:

On Thu, Nov 06, 2025 at 07:42:23PM +0530, Swamil Jain wrote:
> From: Louis Chauvet <louis.chauvet@bootlin.com>
> 
> The dt-bindings for the display, specifically ti,am65x-dss, need to
> include a clock property for data edge synchronization. The current

clock properties are called "clocks". Please rephrase commit msg or use
proper clocks to indicate you access here a clock (if that's the case).

> implementation does not correctly apply the data edge sampling property.

Where is "data edge sampling property"? I do not see it in this binding.

> 
> To address this, synchronization of writes to two different registers is

How this binding achieves that "synchronization"? What are you even
describing here?

> required: one in the TIDSS IP (which is already described in the tidss
> node) and one is in the Memory Mapped Control Register Modules.
> 
> As the Memory Mapped Control Register Modules is located in a different

And now another therm - MMCR...

This commit msg is barely parseable - language is correct but it is a
mix of completely wrong terms.

In case you used LLM to write this - don't. Ever.

> IP, we need to use a phandle to write values in its registers.
> 
> Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
> Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")

You still did not describe the actual bug being fixed here.

> Cc: stable@vger.kernel.org

Best regards,
Krzysztof

On 07/11/2025 08:54, Krzysztof Kozlowski wrote:
> On Thu, Nov 06, 2025 at 07:42:23PM +0530, Swamil Jain wrote:
>> From: Louis Chauvet <louis.chauvet@bootlin.com>
>>
>> The dt-bindings for the display, specifically ti,am65x-dss, need to
>> include a clock property for data edge synchronization. The current
> 
> clock properties are called "clocks". Please rephrase commit msg or use
> proper clocks to indicate you access here a clock (if that's the case).
> 
>> implementation does not correctly apply the data edge sampling property.
> 
> Where is "data edge sampling property"? I do not see it in this binding.
> 
>>
>> To address this, synchronization of writes to two different registers is
> 
> How this binding achieves that "synchronization"? What are you even
> describing here?
> 
>> required: one in the TIDSS IP (which is already described in the tidss
>> node) and one is in the Memory Mapped Control Register Modules.
>>
>> As the Memory Mapped Control Register Modules is located in a different
> 
> And now another therm - MMCR...
> 
> This commit msg is barely parseable - language is correct but it is a
> mix of completely wrong terms.
> 
> In case you used LLM to write this - don't. Ever.
> 
>> IP, we need to use a phandle to write values in its registers.
>>
>> Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
>> Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")
> 
> You still did not describe the actual bug being fixed here.
> 


Actually, NAK, because you ignored entire previous feedback!

Best regards,
Krzysztof