Enable Phy link status pin for boards which support this feature.
Signed-off-by: Michael Dege <michael.dege@renesas.com>
---
drivers/net/ethernet/renesas/rswitch.h | 1 +
drivers/net/ethernet/renesas/rswitch_main.c | 12 ++++++++++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/renesas/rswitch.h b/drivers/net/ethernet/renesas/rswitch.h
index 8168c4cc83fe..a65ba10ae435 100644
--- a/drivers/net/ethernet/renesas/rswitch.h
+++ b/drivers/net/ethernet/renesas/rswitch.h
@@ -960,6 +960,7 @@ struct rswitch_etha {
u8 mac_addr[MAX_ADDR_LEN];
int link;
int speed;
+ bool link_pin;
/* This hardware could not be initialized twice so that marked
* this flag to avoid multiple initialization.
diff --git a/drivers/net/ethernet/renesas/rswitch_main.c b/drivers/net/ethernet/renesas/rswitch_main.c
index 8d8acc2124b8..dd9a0e7a9d74 100644
--- a/drivers/net/ethernet/renesas/rswitch_main.c
+++ b/drivers/net/ethernet/renesas/rswitch_main.c
@@ -1192,9 +1192,15 @@ static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)
static void rswitch_etha_enable_mii(struct rswitch_etha *etha)
{
- rswitch_modify(etha->addr, MPIC, MPIC_PSMCS | MPIC_PSMHT,
+ /* PSMCT: PHY station Management capture adjustment in clk cycles */
+ /* PSMHT: PHY Station Management Hold Time adjustment in clk cycles */
+ /* PSMCS: PHY Station Management Clock selection (clk divider) */
+ /* PLSPP: PHY Link Status Pin Plugged */
+
+ rswitch_modify(etha->addr, MPIC, MPIC_PSMCS | MPIC_PSMHT | MPIC_PLSPP,
FIELD_PREP(MPIC_PSMCS, etha->psmcs) |
- FIELD_PREP(MPIC_PSMHT, 0x06));
+ FIELD_PREP(MPIC_PSMHT, 0x06) |
+ FIELD_PREP(MPIC_PLSPP, etha->link_pin));
}
static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac)
@@ -1338,6 +1344,8 @@ static int rswitch_etha_get_params(struct rswitch_device *rdev)
if (err)
return err;
+ rdev->etha->link_pin = of_property_read_bool(rdev->np_port, "link-pin");
+
err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed);
if (!err) {
rdev->etha->speed = max_speed;
--
2.43.0