Compared to the previously supported RZ/V2H, the Renesas RZ/T2H
(R9A09G077) and RZ/N2H (R9A09G087) SoCs have a smaller FIFO, no resets,
and only two clocks: PCLKSPIn and PCLK. PCLKSPIn, being the clock from
which the SPI transfer clock is generated, is the equivalent of the TCLK
from V2H. They also support generating the SPI transfer clock from PCLK.

V3:
 * no changes

V2:
 * fix missing unwind goto quit_resets
 * add resets: false and reset-names: false

Cosmin Tanislav (14):
  clk: renesas: r9a09g077: add SPI module clocks
  spi: rzv2h-rspi: make resets optional
  spi: rzv2h-rspi: make FIFO size chip-specific
  spi: rzv2h-rspi: make clocks chip-specific
  spi: rzv2h-rspi: move register writes out of rzv2h_rspi_setup_clock()
  spi: rzv2h-rspi: avoid recomputing transfer frequency
  spi: rzv2h-rspi: make transfer clock rate finding chip-specific
  spi: rzv2h-rspi: add support for using PCLK for transfer clock
  spi: rzv2h-rspi: add support for variable transfer clock
  spi: rzv2h-rspi: add support for loopback mode
  dt-bindings: spi: renesas,rzv2h-rspi: document RZ/T2H and RZ/N2H
  spi: rzv2h-rspi: add support for RZ/T2H and RZ/N2H
  arm64: dts: renesas: r9a09g077: Add SPIs support
  arm64: dts: renesas: r9a09g087: Add SPIs support

 .../bindings/spi/renesas,rzv2h-rspi.yaml      |  65 +++-
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi    |  72 ++++
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi    |  72 ++++
 drivers/clk/renesas/r9a09g077-cpg.c           |  22 ++
 drivers/spi/spi-rzv2h-rspi.c                  | 339 +++++++++++++++---
 5 files changed, 501 insertions(+), 69 deletions(-)

-- 
2.51.2