Add support for the four SPI peripherals on the Renesas RZ/T2H Soc.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 72 ++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 42ee9f299837..4f0315235050 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -188,6 +188,78 @@ sci5: serial@81005000 {
status = "disabled";
};
+ rspi0: spi@80007000 {
+ compatible = "renesas,r9a09g077-rspi";
+ reg = <0x0 0x80007000 0x0 0x400>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>,
+ <&cpg CPG_MOD 104>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi1: spi@80007400 {
+ compatible = "renesas,r9a09g077-rspi";
+ reg = <0x0 0x80007400 0x0 0x400>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>,
+ <&cpg CPG_MOD 105>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi2: spi@80007800 {
+ compatible = "renesas,r9a09g077-rspi";
+ reg = <0x0 0x80007800 0x0 0x400>;
+ interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>,
+ <&cpg CPG_MOD 106>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi3: spi@81007000 {
+ compatible = "renesas,r9a09g077-rspi";
+ reg = <0x0 0x81007000 0x0 0x400>;
+ interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>,
+ <&cpg CPG_MOD 602>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
wdt0: watchdog@80082000 {
compatible = "renesas,r9a09g077-wdt";
reg = <0 0x80082000 0 0x400>,
--
2.51.2