drivers/pci/controller/dwc/pci-meson.c | 17 ----------------- drivers/pci/probe.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 17 deletions(-)
Current PCIe initialization exhibits a key optimization gap: Root Ports may operate with non-optimal Maximum Payload Size (MPS) settings. While downstream device configuration is handled during bus enumeration, Root Port MPS values inherited from firmware or hardware defaults often fail to utilize the full capabilities supported by controller hardware. This results in suboptimal data transfer efficiency throughout the PCIe hierarchy. This patch series addresses this by: 1. Core PCI enhancement (Patch 1): - Proactively configures Root Port MPS during host controller probing - Sets initial MPS to hardware maximum (128 << dev->pcie_mpss) - Conditional on PCIe bus tuning being enabled (PCIE_BUS_TUNE_OFF unset) - Maintains backward compatibility via PCIE_BUS_TUNE_OFF check - Preserves standard MPS negotiation during downstream enumeration 2. Driver cleanup (Patch 2): - Removes redundant MPS configuration from Meson PCIe controller driver - Functionality is now centralized in PCI core - Simplifies driver maintenance long-term --- Changes for v6: - Modify the commit message and comments. (Bjorn) - Patch 1/2 code logic: Add !bridge check to configure MPS only for Root Ports without an upstream bridge (root bridges), avoiding incorrect handling of non-root-bridge Root Ports (Niklas). Changes for v5: https://patchwork.kernel.org/project/linux-pci/patch/20250620155507.1022099-1-18255117159@163.com/ - Use pcie_set_mps directly instead of pcie_write_mps. - The patch 1 commit message were modified. Changes for v4: https://patchwork.kernel.org/project/linux-pci/patch/20250510155607.390687-1-18255117159@163.com/ - The patch [v4 1/2] add a comment to explain why it was done this way. - The patch [v4 2/2] have not been modified. - Drop patch [v3 3/3]. The Maintainer of the pci-aardvark.c file suggests that this patch cannot be submitted. In addition, Mani also suggests dropping this patch until this series of issues is resolved. Changes for v3: https://patchwork.kernel.org/project/linux-pci/patch/20250506173439.292460-1-18255117159@163.com/ - The new split is patch 2/3 and 3/3. - Modify the patch 1/3 according to Niklas' suggestion. Changes for v2: https://patchwork.kernel.org/project/linux-pci/patch/20250425095708.32662-1-18255117159@163.com/ - According to the Maintainer's suggestion, limit the setting of MPS changes to platforms with controller drivers. - Delete the MPS code set by the SOC manufacturer. --- Hans Zhang (2): PCI: Configure Root Port MPS during host probing PCI: dwc: Remove redundant MPS configuration drivers/pci/controller/dwc/pci-meson.c | 17 ----------------- drivers/pci/probe.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 17 deletions(-) base-commit: 691d401c7e0e5ea34ac6f8151bc0696db1b2500a -- 2.34.1
On Wed, Nov 05, 2025 at 12:51:23AM +0800, Hans Zhang wrote: > Current PCIe initialization exhibits a key optimization gap: Root Ports > may operate with non-optimal Maximum Payload Size (MPS) settings. While > downstream device configuration is handled during bus enumeration, Root > Port MPS values inherited from firmware or hardware defaults often fail > to utilize the full capabilities supported by controller hardware. This > results in suboptimal data transfer efficiency throughout the PCIe > hierarchy. Hello PCI maintainers, Merge window is opening soon, what is the status of this series? Kind regards, Niklas
On 04-11-2025 22:21, Hans Zhang wrote: > Current PCIe initialization exhibits a key optimization gap: Root Ports > may operate with non-optimal Maximum Payload Size (MPS) settings. While > downstream device configuration is handled during bus enumeration, Root > Port MPS values inherited from firmware or hardware defaults often fail > to utilize the full capabilities supported by controller hardware. This > results in suboptimal data transfer efficiency throughout the PCIe > hierarchy. > > This patch series addresses this by: > > 1. Core PCI enhancement (Patch 1): > - Proactively configures Root Port MPS during host controller probing > - Sets initial MPS to hardware maximum (128 << dev->pcie_mpss) > - Conditional on PCIe bus tuning being enabled (PCIE_BUS_TUNE_OFF unset) > - Maintains backward compatibility via PCIE_BUS_TUNE_OFF check > - Preserves standard MPS negotiation during downstream enumeration > > 2. Driver cleanup (Patch 2): > - Removes redundant MPS configuration from Meson PCIe controller driver > - Functionality is now centralized in PCI core > - Simplifies driver maintenance long-term > > --- > Changes for v6: > - Modify the commit message and comments. (Bjorn) > - Patch 1/2 code logic: Add !bridge check to configure MPS only for Root Ports > without an upstream bridge (root bridges), avoiding incorrect handling of > non-root-bridge Root Ports (Niklas). Tested this patch series on Agilex 7. Tested-by: Mahesh Vaidya <mahesh.vaidya@altera.com> > > Changes for v5: > https://patchwork.kernel.org/project/linux-pci/patch/20250620155507.1022099-1-18255117159@163.com/ > > - Use pcie_set_mps directly instead of pcie_write_mps. > - The patch 1 commit message were modified. > > Changes for v4: > https://patchwork.kernel.org/project/linux-pci/patch/20250510155607.390687-1-18255117159@163.com/ > > - The patch [v4 1/2] add a comment to explain why it was done this way. > - The patch [v4 2/2] have not been modified. > - Drop patch [v3 3/3]. The Maintainer of the pci-aardvark.c file suggests > that this patch cannot be submitted. In addition, Mani also suggests > dropping this patch until this series of issues is resolved. > > Changes for v3: > https://patchwork.kernel.org/project/linux-pci/patch/20250506173439.292460-1-18255117159@163.com/ > > - The new split is patch 2/3 and 3/3. > - Modify the patch 1/3 according to Niklas' suggestion. > > Changes for v2: > https://patchwork.kernel.org/project/linux-pci/patch/20250425095708.32662-1-18255117159@163.com/ > > - According to the Maintainer's suggestion, limit the setting of MPS > changes to platforms with controller drivers. > - Delete the MPS code set by the SOC manufacturer. > --- > > Hans Zhang (2): > PCI: Configure Root Port MPS during host probing > PCI: dwc: Remove redundant MPS configuration > > drivers/pci/controller/dwc/pci-meson.c | 17 ----------------- > drivers/pci/probe.c | 12 ++++++++++++ > 2 files changed, 12 insertions(+), 17 deletions(-) > > > base-commit: 691d401c7e0e5ea34ac6f8151bc0696db1b2500a
On 11/12/2025 4:06 PM, Mahesh Vaidya wrote: > [You don't often get email from mahesh.vaidya@altera.com. Learn why this > is important at https://aka.ms/LearnAboutSenderIdentification ] > > EXTERNAL EMAIL > > On 04-11-2025 22:21, Hans Zhang wrote: >> Current PCIe initialization exhibits a key optimization gap: Root Ports >> may operate with non-optimal Maximum Payload Size (MPS) settings. While >> downstream device configuration is handled during bus enumeration, Root >> Port MPS values inherited from firmware or hardware defaults often fail >> to utilize the full capabilities supported by controller hardware. This >> results in suboptimal data transfer efficiency throughout the PCIe >> hierarchy. >> >> This patch series addresses this by: >> >> 1. Core PCI enhancement (Patch 1): >> - Proactively configures Root Port MPS during host controller probing >> - Sets initial MPS to hardware maximum (128 << dev->pcie_mpss) >> - Conditional on PCIe bus tuning being enabled (PCIE_BUS_TUNE_OFF unset) >> - Maintains backward compatibility via PCIE_BUS_TUNE_OFF check >> - Preserves standard MPS negotiation during downstream enumeration >> >> 2. Driver cleanup (Patch 2): >> - Removes redundant MPS configuration from Meson PCIe controller driver >> - Functionality is now centralized in PCI core >> - Simplifies driver maintenance long-term >> >> --- >> Changes for v6: >> - Modify the commit message and comments. (Bjorn) >> - Patch 1/2 code logic: Add !bridge check to configure MPS only for >> Root Ports >> without an upstream bridge (root bridges), avoiding incorrect >> handling of >> non-root-bridge Root Ports (Niklas). > Tested this patch series on Agilex 7. > > Tested-by: Mahesh Vaidya <mahesh.vaidya@altera.com> > Hi Mahesh, Thank you for your test. Best regards, Hans >> >> Changes for v5: >> https://patchwork.kernel.org/project/linux-pci/ >> patch/20250620155507.1022099-1-18255117159@163.com/ >> >> - Use pcie_set_mps directly instead of pcie_write_mps. >> - The patch 1 commit message were modified. >> >> Changes for v4: >> https://patchwork.kernel.org/project/linux-pci/ >> patch/20250510155607.390687-1-18255117159@163.com/ >> >> - The patch [v4 1/2] add a comment to explain why it was done this way. >> - The patch [v4 2/2] have not been modified. >> - Drop patch [v3 3/3]. The Maintainer of the pci-aardvark.c file suggests >> that this patch cannot be submitted. In addition, Mani also suggests >> dropping this patch until this series of issues is resolved. >> >> Changes for v3: >> https://patchwork.kernel.org/project/linux-pci/ >> patch/20250506173439.292460-1-18255117159@163.com/ >> >> - The new split is patch 2/3 and 3/3. >> - Modify the patch 1/3 according to Niklas' suggestion. >> >> Changes for v2: >> https://patchwork.kernel.org/project/linux-pci/ >> patch/20250425095708.32662-1-18255117159@163.com/ >> >> - According to the Maintainer's suggestion, limit the setting of MPS >> changes to platforms with controller drivers. >> - Delete the MPS code set by the SOC manufacturer. >> --- >> >> Hans Zhang (2): >> PCI: Configure Root Port MPS during host probing >> PCI: dwc: Remove redundant MPS configuration >> >> drivers/pci/controller/dwc/pci-meson.c | 17 ----------------- >> drivers/pci/probe.c | 12 ++++++++++++ >> 2 files changed, 12 insertions(+), 17 deletions(-) >> >> >> base-commit: 691d401c7e0e5ea34ac6f8151bc0696db1b2500a >
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