When timer is fired in oneshot mode, CSR TVAL will stop with value -1
rather than 0. However when register CSR TVAL is restored, it will
continue to count down rather than stop there.

Now the method is to write 0 to CSR TVAL, wait to count down for 1
cycle at least, which is 10ns with timer freq 100MHZ, and retore timer
interrupt status. Here add 2 cycles delay to assure that timer interrupt
is injected.

With this patch, timer selftest case passes to run always.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 arch/loongarch/kvm/timer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/loongarch/kvm/timer.c b/arch/loongarch/kvm/timer.c
index 32dc213374be..daf1b60a8d47 100644
--- a/arch/loongarch/kvm/timer.c
+++ b/arch/loongarch/kvm/timer.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
  */
 
+#include <asm/delay.h>
 #include <linux/kvm_host.h>
 #include <asm/kvm_csr.h>
 #include <asm/kvm_vcpu.h>
@@ -95,6 +96,8 @@ void kvm_restore_timer(struct kvm_vcpu *vcpu)
 		 * and set CSR TVAL with -1
 		 */
 		write_gcsr_timertick(0);
+		/* wait more than 1 cycle until timer interrupt injected */
+		__delay(2);
 
 		/*
 		 * Writing CSR_TINTCLR_TI to LOONGARCH_CSR_TINTCLR will clear

base-commit: ec0b62ccc986c06552c57f54116171cfd186ef92
-- 
2.39.3

Applied, thanks.

Huacai

On Tue, Nov 4, 2025 at 7:47 PM Bibo Mao <maobibo@loongson.cn> wrote:
>
> When timer is fired in oneshot mode, CSR TVAL will stop with value -1
> rather than 0. However when register CSR TVAL is restored, it will
> continue to count down rather than stop there.
>
> Now the method is to write 0 to CSR TVAL, wait to count down for 1
> cycle at least, which is 10ns with timer freq 100MHZ, and retore timer
> interrupt status. Here add 2 cycles delay to assure that timer interrupt
> is injected.
>
> With this patch, timer selftest case passes to run always.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>  arch/loongarch/kvm/timer.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/loongarch/kvm/timer.c b/arch/loongarch/kvm/timer.c
> index 32dc213374be..daf1b60a8d47 100644
> --- a/arch/loongarch/kvm/timer.c
> +++ b/arch/loongarch/kvm/timer.c
> @@ -3,6 +3,7 @@
>   * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
>   */
>
> +#include <asm/delay.h>
>  #include <linux/kvm_host.h>
>  #include <asm/kvm_csr.h>
>  #include <asm/kvm_vcpu.h>
> @@ -95,6 +96,8 @@ void kvm_restore_timer(struct kvm_vcpu *vcpu)
>                  * and set CSR TVAL with -1
>                  */
>                 write_gcsr_timertick(0);
> +               /* wait more than 1 cycle until timer interrupt injected */
> +               __delay(2);
>
>                 /*
>                  * Writing CSR_TINTCLR_TI to LOONGARCH_CSR_TINTCLR will clear
>
> base-commit: ec0b62ccc986c06552c57f54116171cfd186ef92
> --
> 2.39.3
>
>