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[PATCH v3] dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock

Konrad Dybcio posted 1 patch 1 month, 2 weeks ago 
Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 4 ++++
1 file changed, 4 insertions(+)
[PATCH v3] dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock
Posted by Konrad Dybcio 1 month, 2 weeks ago 
From: Konrad Dybcio <konrad.dybcio@linaro.org>

Some IOMMUs on some platforms (there doesn't seem to be a good denominator
for this) require the presence of a third clock, specifically relating
to the instance's Translation Buffer Unit (TBU).

Stephan Gerhold noted [1] that according to Qualcomm Snapdragon 410E
Processor (APQ8016E) Technical Reference Manual, SMMU chapter, section
"8.8.3.1.2 Clock gating", which reads:

For APPS TCU/TBU (TBU to TCU interface is asynchronous)
Software should turn ON clock to APPS TCU
  - During APPS TCU register programming sequence

For GPU TCU/TBU (TBU to TCU interface is synchronous)
Software should turn ON clock to GPU TBU
  - During GPU TLB invalidation sequence <=====================
Software should turn ON clock to GPU TCU
  - During GPU TCU register programming sequence
  - While GPU master clock is Active

The clock should be turned on at least during TLB invalidation on the
GPU SMMU instance. This is corroborated by Commit 5bc1cf1466f6
("iommu/qcom: add optional 'tbu' clock for TLB invalidate").

This is also not to be confused with qcom,sdm845-tbu, which is a
description of a debug interface, absent on the generation of hardware
that this binding describes.

Allow this clock.

[1] https://lore.kernel.org/linux-arm-msm/aPX_cKtial56AgvU@linaro.org/

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Changes in v3:
- Expand the commit message
- Link to v2: https://lore.kernel.org/r/20251015-topic-qciommu_bindings_fix-v2-1-a0f3c705d0f3@oss.qualcomm.com
Changes in v2:
- Resending from a 2023 megaseries, no changes
- Link to v1: https://lore.kernel.org/lkml/20230627-topic-more_bindings-v1-7-6b4b6cd081e5@linaro.org/
---
 Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
index 3e5623edd207..93a489025317 100644
--- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
@@ -32,14 +32,18 @@ properties:
           - const: qcom,msm-iommu-v2
 
   clocks:
+    minItems: 2
     items:
       - description: Clock required for IOMMU register group access
       - description: Clock required for underlying bus access
+      - description: Clock required for Translation Buffer Unit access
 
   clock-names:
+    minItems: 2
     items:
       - const: iface
       - const: bus
+      - const: tbu
 
   power-domains:
     maxItems: 1

---
base-commit: 12132ce56439eaefea25c647d850eeed99179d88
change-id: 20251015-topic-qciommu_bindings_fix-3bf3904041b9

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Re: [PATCH v3] dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock
Posted by Will Deacon 3 weeks, 4 days ago 
On Tue, 04 Nov 2025 15:47:26 +0100, Konrad Dybcio wrote:
> Some IOMMUs on some platforms (there doesn't seem to be a good denominator
> for this) require the presence of a third clock, specifically relating
> to the instance's Translation Buffer Unit (TBU).
> 
> Stephan Gerhold noted [1] that according to Qualcomm Snapdragon 410E
> Processor (APQ8016E) Technical Reference Manual, SMMU chapter, section
> "8.8.3.1.2 Clock gating", which reads:
> 
> [...]

Applied to iommu (arm/smmu/bindings), thanks!

[1/1] dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock
      https://git.kernel.org/iommu/c/fe6262910cd3

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
Re: [PATCH v3] dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock
Posted by Bjorn Andersson 1 month, 1 week ago 
On Tue, Nov 04, 2025 at 03:47:26PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> Some IOMMUs on some platforms (there doesn't seem to be a good denominator
> for this) require the presence of a third clock, specifically relating
> to the instance's Translation Buffer Unit (TBU).
> 
> Stephan Gerhold noted [1] that according to Qualcomm Snapdragon 410E
> Processor (APQ8016E) Technical Reference Manual, SMMU chapter, section
> "8.8.3.1.2 Clock gating", which reads:
> 
> For APPS TCU/TBU (TBU to TCU interface is asynchronous)
> Software should turn ON clock to APPS TCU
>   - During APPS TCU register programming sequence
> 
> For GPU TCU/TBU (TBU to TCU interface is synchronous)
> Software should turn ON clock to GPU TBU
>   - During GPU TLB invalidation sequence <=====================
> Software should turn ON clock to GPU TCU
>   - During GPU TCU register programming sequence
>   - While GPU master clock is Active
> 
> The clock should be turned on at least during TLB invalidation on the
> GPU SMMU instance. This is corroborated by Commit 5bc1cf1466f6
> ("iommu/qcom: add optional 'tbu' clock for TLB invalidate").
> 
> This is also not to be confused with qcom,sdm845-tbu, which is a
> description of a debug interface, absent on the generation of hardware
> that this binding describes.
> 
> Allow this clock.
> 
> [1] https://lore.kernel.org/linux-arm-msm/aPX_cKtial56AgvU@linaro.org/
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Bjorn Andersson <andersson@kernel.org>

Regards,
Bjorn

> ---
> Changes in v3:
> - Expand the commit message
> - Link to v2: https://lore.kernel.org/r/20251015-topic-qciommu_bindings_fix-v2-1-a0f3c705d0f3@oss.qualcomm.com
> Changes in v2:
> - Resending from a 2023 megaseries, no changes
> - Link to v1: https://lore.kernel.org/lkml/20230627-topic-more_bindings-v1-7-6b4b6cd081e5@linaro.org/
> ---
>  Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
> index 3e5623edd207..93a489025317 100644
> --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
> @@ -32,14 +32,18 @@ properties:
>            - const: qcom,msm-iommu-v2
>  
>    clocks:
> +    minItems: 2
>      items:
>        - description: Clock required for IOMMU register group access
>        - description: Clock required for underlying bus access
> +      - description: Clock required for Translation Buffer Unit access
>  
>    clock-names:
> +    minItems: 2
>      items:
>        - const: iface
>        - const: bus
> +      - const: tbu
>  
>    power-domains:
>      maxItems: 1
> 
> ---
> base-commit: 12132ce56439eaefea25c647d850eeed99179d88
> change-id: 20251015-topic-qciommu_bindings_fix-3bf3904041b9
> 
> Best regards,
> -- 
> Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
>

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