arch/arm64/boot/dts/qcom/kodiak.dtsi | 290 +++++++++++++++++++++++++++++++++++ 1 file changed, 290 insertions(+)
Add TPDM, TPDA, CTI and funnel coresight devices for AOSS and QDSS
blocks.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 290 +++++++++++++++++++++++++++++++++++
1 file changed, 290 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 3ef61af2ed8a..09aba1645408 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -3338,6 +3338,85 @@ stm_out: endpoint {
};
};
+ tpda@6004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x06004000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1c {
+ reg = <28>;
+ qdss_tpda_in28: endpoint {
+ remote-endpoint = <&spdm_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_tpda_out: endpoint {
+ remote-endpoint = <&qdss_dl_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@6005000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x06005000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ qdss_dl_funnel_in0: endpoint {
+ remote-endpoint = <&qdss_tpda_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_dl_funnel_out: endpoint {
+ remote-endpoint = <&funnel0_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@600f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x0600f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ spdm_tpdm_out: endpoint {
+ remote-endpoint = <&qdss_tpda_in28>;
+ };
+ };
+ };
+ };
+
+ cti@6010000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x06010000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
funnel@6041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06041000 0 0x1000>;
@@ -3357,6 +3436,14 @@ in-ports {
#address-cells = <1>;
#size-cells = <0>;
+ port@6 {
+ reg = <6>;
+
+ funnel0_in6: endpoint {
+ remote-endpoint = <&qdss_dl_funnel_out>;
+ };
+ };
+
port@7 {
reg = <7>;
funnel0_in7: endpoint {
@@ -3471,6 +3558,38 @@ etr_in: endpoint {
};
};
+ cti@6b00000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x06b00000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ cti@6b01000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x06b01000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ cti@6b02000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x06b02000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ cti@6b03000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x06b03000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
funnel@6b04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06b04000 0 0x1000>;
@@ -3490,6 +3609,13 @@ in-ports {
#address-cells = <1>;
#size-cells = <0>;
+ port@6 {
+ reg = <6>;
+ swao_funnel_in6: endpoint {
+ remote-endpoint = <&aoss_tpda_out>;
+ };
+ };
+
port@7 {
reg = <7>;
swao_funnel_in: endpoint {
@@ -3548,6 +3674,170 @@ swao_replicator_in: endpoint {
};
};
+ tpda@6b08000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x06b08000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ aoss_tpda_in0: endpoint {
+ remote-endpoint = <&swao_prio0_tpdm_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ aoss_tpda_in1: endpoint {
+ remote-endpoint = <&swao_prio1_tpdm_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ aoss_tpda_in2: endpoint {
+ remote-endpoint = <&swao_prio2_tpdm_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ aoss_tpda_in3: endpoint {
+ remote-endpoint = <&swao_prio3_tpdm_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ aoss_tpda_in4: endpoint {
+ remote-endpoint = <&swao_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ aoss_tpda_out: endpoint {
+ remote-endpoint = <&swao_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@6b09000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x06b09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio0_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@6b0a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x06b0a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio1_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@6b0b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x06b0b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio2_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@6b0c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x06b0c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio3_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@6b0d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x06b0d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in4>;
+ };
+ };
+ };
+ };
+
+ cti@6b11000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x06b11000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
---
base-commit: 20e1dca0f0d16ca3f0937a5969a789addedc0f29
change-id: 20251103-add-coresight-nodes-for-sc7280-60ceb4dc274d
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>On 11/3/25 9:35 AM, Jie Gan wrote:
> Add TPDM, TPDA, CTI and funnel coresight devices for AOSS and QDSS
> blocks.
>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kodiak.dtsi | 290 +++++++++++++++++++++++++++++++++++
> 1 file changed, 290 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> index 3ef61af2ed8a..09aba1645408 100644
> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> @@ -3338,6 +3338,85 @@ stm_out: endpoint {
> };
> };
>
> + tpda@6004000 {
> + compatible = "qcom,coresight-tpda", "arm,primecell";
> + reg = <0x0 0x06004000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1c {
> + reg = <28>;
Please use hex in 'reg' (just like you did in the unit address above)
> + qdss_tpda_in28: endpoint {
and leave a \n between the last property and the following subnodes
[...]
> + cti@6010000 {
> + compatible = "arm,coresight-cti", "arm,primecell";
> + reg = <0x0 0x06010000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
I see 15 more CTI instances following this one at a 0x1000 stride,
followed by a TPIU at 0x06040000.
Actually a whole lot more debugging hardware. This patchset looks
tailored for debugging AOSS< as you briefly mentioned in the commit
message.
Would it be beneficial or useful to (perhaps in a separate series)
extend the support for those?
FWIW the various register bases and field sizes correspond to what I
can see in the docs, I can't speak for the port numbers. Please just
fix up the style issues I mentioned above.
Konrad
On 11/3/2025 9:15 PM, Konrad Dybcio wrote:
> On 11/3/25 9:35 AM, Jie Gan wrote:
>> Add TPDM, TPDA, CTI and funnel coresight devices for AOSS and QDSS
>> blocks.
>>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kodiak.dtsi | 290 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 290 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> index 3ef61af2ed8a..09aba1645408 100644
>> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> @@ -3338,6 +3338,85 @@ stm_out: endpoint {
>> };
>> };
>>
>> + tpda@6004000 {
>> + compatible = "qcom,coresight-tpda", "arm,primecell";
>> + reg = <0x0 0x06004000 0x0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@1c {
>> + reg = <28>;
>
> Please use hex in 'reg' (just like you did in the unit address above)
>
>> + qdss_tpda_in28: endpoint {
>
> and leave a \n between the last property and the following subnodes
>
> [...]
>
will fix it.
>
>> + cti@6010000 {
>> + compatible = "arm,coresight-cti", "arm,primecell";
>> + reg = <0x0 0x06010000 0x0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>
> I see 15 more CTI instances following this one at a 0x1000 stride,
> followed by a TPIU at 0x06040000.
>
I defined this CTI device solely because it manages debug behaviors for
STM, ETF, and ETR devices, which are already supported in the upstream
kernel.
For other CTI devices in QDSS block, they are related to other blocks
which are not included in current patch. May introduce them in the future.
Thanks,
Jie
> Actually a whole lot more debugging hardware. This patchset looks
> tailored for debugging AOSS< as you briefly mentioned in the commit
> message.
>
> Would it be beneficial or useful to (perhaps in a separate series)
> extend the support for those?
>
> FWIW the various register bases and field sizes correspond to what I
> can see in the docs, I can't speak for the port numbers. Please just
> fix up the style issues I mentioned above.
>
> Konrad
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