From: "jun.guo" <jun.guo@cixtech.com>

The Cadence SPI IP supports configurable FIFO data widths during
integration. On some SoCs, the FIFO data width is designed to be 16 or
32 bits at the chip design stage. However, the current driver only
supports communication with an 8-bit FIFO data width. Therefore, these
patches are added to enable the driver to support communication with
16-bit and 32-bit FIFO data widths.

This series introduces the following enhancements for Cadence SPI
controller support on arm64 platforms:

Patch 1: Add a compatible string "cix,sky1-spi-r1p6" for the cix
sky1 SoC.
Patch 2: Update DT binding docs to support cix sky1 SoC.
Patch 3: Enhance the SPI Cadence driver to support data transmission
with bits_per_word values of 16 and 32.

The CIX Sky1 SPI supported patch is added:
https://lore.kernel.org/all/20250919013118.853078-1-jun.guo@cixtech.com/

The patches have been tested on CIX SKY1 platform.

Changes for v3:
- Rebase the dt-bindings modification on top of the latest patches in
  spi/for-next to make the patch more minimal. 

Changes for v2:
- Remove the fifo-width property and add a compatible string for the
  cix sky1 SoC to control the FIFO data width configuration.

Jun Guo (3):
  dt-bindings: spi: spi-cadence: update DT binding docs to support cix
    sky1 SoC
  spi: spi-cadence: supports transmission with bits_per_word of 16 and
    32
  arm64: dts: cix: add a compatible string for the cix sky1 SoC

 .../devicetree/bindings/spi/spi-cadence.yaml  |   1 +
 arch/arm64/boot/dts/cix/sky1.dtsi             |   4 +-
 drivers/spi/spi-cadence.c                     | 106 +++++++++++++++---
 3 files changed, 96 insertions(+), 15 deletions(-)

-- 
2.34.1

On Fri, 31 Oct 2025 15:30:00 +0800, Jun Guo wrote:
> The Cadence SPI IP supports configurable FIFO data widths during
> integration. On some SoCs, the FIFO data width is designed to be 16 or
> 32 bits at the chip design stage. However, the current driver only
> supports communication with an 8-bit FIFO data width. Therefore, these
> patches are added to enable the driver to support communication with
> 16-bit and 32-bit FIFO data widths.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/3] dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC
      commit: 55b5d192bab5e152bda8f8cefe837c4ed0ec60c5
[2/3] spi: spi-cadence: supports transmission with bits_per_word of 16 and 32
      commit: 4e00135b2dd1d7924a58bffa551b6ceb3bd836f2

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark