Correct instruction spelling errors.

Signed-off-by: Chu Guangqing <chuguangqing@inspur.com>
---
 tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
index 4cc50b7da526..4001cc5753a7 100644
--- a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
@@ -81,7 +81,7 @@
         "BriefDescription": "L2D TLB access"
     },
     {
-        "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count",
+        "PublicDescription": "Level 2 access to instruction TLB that caused a page table walk. This event counts on any instruction access which causes L2I_TLB_REFILL to count",
         "EventCode": "0x35",
         "EventName": "L2I_TLB_ACCESS",
         "BriefDescription": "L2I TLB access"
-- 
2.43.7

On Fri, 31 Oct 2025 11:17:29 +0800, Chu Guangqing wrote:
> Correct instruction spelling errors.
> 
> 
Applied to perf-tools-next, thanks!

Best regards,
Namhyung

On Fri, 31 Oct 2025, Chu Guangqing wrote:
> Correct instruction spelling errors.
>
> Signed-off-by: Chu Guangqing <chuguangqing@inspur.com>


Thanks for the patch. Just one comment, would you mind changing the 
subject line slightly. Something like

"perf vendor events arm64: Fix typo in Ampere eMag json file"


With that change

Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>

Cheers, Ilkka


> ---
> tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
> index 4cc50b7da526..4001cc5753a7 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
> @@ -81,7 +81,7 @@
>         "BriefDescription": "L2D TLB access"
>     },
>     {
> -        "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count",
> +        "PublicDescription": "Level 2 access to instruction TLB that caused a page table walk. This event counts on any instruction access which causes L2I_TLB_REFILL to count",
>         "EventCode": "0x35",
>         "EventName": "L2I_TLB_ACCESS",
>         "BriefDescription": "L2I TLB access"
> -- 
> 2.43.7
>
>
>

Hello,

On Fri, Oct 31, 2025 at 12:25:37PM -0700, Ilkka Koskinen wrote:
> 
> On Fri, 31 Oct 2025, Chu Guangqing wrote:
> > Correct instruction spelling errors.
> > 
> > Signed-off-by: Chu Guangqing <chuguangqing@inspur.com>
> 
> 
> Thanks for the patch. Just one comment, would you mind changing the subject
> line slightly. Something like
> 
> "perf vendor events arm64: Fix typo in Ampere eMag json file"
> 
> 
> With that change
> 
> Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>

Thanks, I'll handle the both changes.
Namhyung

On 31/10/2025 3:17 am, Chu Guangqing wrote:
> Correct instruction spelling errors.
> 
> Signed-off-by: Chu Guangqing <chuguangqing@inspur.com>
> ---
>   tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
> index 4cc50b7da526..4001cc5753a7 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
> @@ -81,7 +81,7 @@
>           "BriefDescription": "L2D TLB access"
>       },
>       {
> -        "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count",
> +        "PublicDescription": "Level 2 access to instruction TLB that caused a page table walk. This event counts on any instruction access which causes L2I_TLB_REFILL to count",
>           "EventCode": "0x35",
>           "EventName": "L2I_TLB_ACCESS",
>           "BriefDescription": "L2I TLB access"

Reviewed-by: James Clark <james.clark@linaro.org>