HAMOA-IOT-EVK board includes a PCIe3 controller and x8 slot that require
proper power rail and control signal configuration. This update adds
`vddpe-3v3-supply` and `regulator-pcie-12v` to provide 3.3V to the PHY
and 12V to the slot for external devices.
It also introduces PM GPIOs to manage power enable and reset signals,
ensuring stable power sequencing and reliable PCIe3 operation.
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 79 ++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
index 24c2dcef0ba8..0984a6eed226 100644
--- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
+++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
@@ -414,6 +414,48 @@ vreg_wwan: regulator-wwan {
regulator-boot-on;
};
+ vreg_pcie_12v: regulator-pcie-12v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_PCIE_12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+
+ gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&pcie_x8_12v>;
+ pinctrl-names = "default";
+ };
+
+ vreg_pcie_3v3_aux: regulator-pcie-3v3-aux {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_PCIE_3P3_AUX";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&pm_sde7_aux_3p3_en>;
+ pinctrl-names = "default";
+ };
+
+ vreg_pcie_3v3: regulator-pcie-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_PCIE_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&pm_sde7_main_3p3_en>;
+ pinctrl-names = "default";
+};
+
sound {
compatible = "qcom,x1e80100-sndcard";
model = "X1E80100-EVK";
@@ -844,6 +886,12 @@ &mdss_dp3_phy {
status = "okay";
};
+&pcie3_port {
+ vpcie12v-supply = <&vreg_pcie_12v>;
+ vpcie3v3-supply = <&vreg_pcie_3v3>;
+ vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>;
+};
+
&pcie5 {
vddpe-3v3-supply = <&vreg_wwan>;
};
@@ -872,6 +920,17 @@ usb0_3p3_reg_en: usb0-3p3-reg-en-state {
};
};
+&pm8550ve_8_gpios {
+ pcie_x8_12v: pcie-12v-default-state {
+ pins = "gpio8";
+ function = "normal";
+ output-enable;
+ output-high;
+ bias-pull-down;
+ power-source = <0>;
+ };
+};
+
&pm8550ve_9_gpios {
usb0_1p8_reg_en: usb0-1p8-reg-en-state {
pins = "gpio8";
@@ -883,6 +942,26 @@ usb0_1p8_reg_en: usb0-1p8-reg-en-state {
};
};
+&pmc8380_3_gpios {
+ pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state {
+ pins = "gpio8";
+ function = "normal";
+ output-enable;
+ output-high;
+ bias-pull-down;
+ power-source = <0>;
+ };
+
+ pm_sde7_main_3p3_en: pcie-main-3p3-default-state {
+ pins = "gpio6";
+ function = "normal";
+ output-enable;
+ output-high;
+ bias-pull-down;
+ power-source = <0>;
+ };
+};
+
&pmc8380_5_gpios {
usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
pins = "gpio8";
--
2.34.1On Thu, Oct 30, 2025 at 04:48:04PM +0800, Ziyue Zhang wrote:
> HAMOA-IOT-EVK board includes a PCIe3 controller and x8 slot that require
> proper power rail and control signal configuration. This update adds
> `vddpe-3v3-supply` and `regulator-pcie-12v` to provide 3.3V to the PHY
> and 12V to the slot for external devices.
>
> It also introduces PM GPIOs to manage power enable and reset signals,
> ensuring stable power sequencing and reliable PCIe3 operation.
I'm afraid I don't understand this paragraph. In the first paragraph you
establish that you have PCIe3, there is a x8 slot, and there's 3.3V and
12V supplies.
But where in the patch do you establish "reset signals" and "ensure
stable power sequencing"?
>
> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 79 ++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
> index 24c2dcef0ba8..0984a6eed226 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
> @@ -414,6 +414,48 @@ vreg_wwan: regulator-wwan {
> regulator-boot-on;
> };
>
> + vreg_pcie_12v: regulator-pcie-12v {
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes
2. Nodes without unit addresses shall be ordered alpha-numerically by
the node name. For a few node types, they can be ordered by the main
property, e.g. pin configuration states ordered by value of “pins”
property.
Regards,
Bjorn
> + compatible = "regulator-fixed";
> +
> + regulator-name = "VREG_PCIE_12V";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> +
> + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-0 = <&pcie_x8_12v>;
> + pinctrl-names = "default";
> + };
> +
> + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux {
> + compatible = "regulator-fixed";
> +
> + regulator-name = "VREG_PCIE_3P3_AUX";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-0 = <&pm_sde7_aux_3p3_en>;
> + pinctrl-names = "default";
> + };
> +
> + vreg_pcie_3v3: regulator-pcie-3v3 {
> + compatible = "regulator-fixed";
> +
> + regulator-name = "VREG_PCIE_3P3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-0 = <&pm_sde7_main_3p3_en>;
> + pinctrl-names = "default";
> +};
> +
> sound {
> compatible = "qcom,x1e80100-sndcard";
> model = "X1E80100-EVK";
> @@ -844,6 +886,12 @@ &mdss_dp3_phy {
> status = "okay";
> };
>
> +&pcie3_port {
> + vpcie12v-supply = <&vreg_pcie_12v>;
> + vpcie3v3-supply = <&vreg_pcie_3v3>;
> + vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>;
> +};
> +
> &pcie5 {
> vddpe-3v3-supply = <&vreg_wwan>;
> };
> @@ -872,6 +920,17 @@ usb0_3p3_reg_en: usb0-3p3-reg-en-state {
> };
> };
>
> +&pm8550ve_8_gpios {
> + pcie_x8_12v: pcie-12v-default-state {
> + pins = "gpio8";
> + function = "normal";
> + output-enable;
> + output-high;
> + bias-pull-down;
> + power-source = <0>;
> + };
> +};
> +
> &pm8550ve_9_gpios {
> usb0_1p8_reg_en: usb0-1p8-reg-en-state {
> pins = "gpio8";
> @@ -883,6 +942,26 @@ usb0_1p8_reg_en: usb0-1p8-reg-en-state {
> };
> };
>
> +&pmc8380_3_gpios {
> + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state {
> + pins = "gpio8";
> + function = "normal";
> + output-enable;
> + output-high;
> + bias-pull-down;
> + power-source = <0>;
> + };
> +
> + pm_sde7_main_3p3_en: pcie-main-3p3-default-state {
> + pins = "gpio6";
> + function = "normal";
> + output-enable;
> + output-high;
> + bias-pull-down;
> + power-source = <0>;
> + };
> +};
> +
> &pmc8380_5_gpios {
> usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
> pins = "gpio8";
> --
> 2.34.1
>
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