.../bindings/fpga/lattice,ice40-fpga-mgr.yaml | 59 +++++++++++++++++++ .../bindings/fpga/lattice-ice40-fpga-mgr.txt | 21 ------- 2 files changed, 59 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ice40-fpga-mgr.yaml delete mode 100644 Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
Convert the lattice,ice40-fpga-mgr binding to DT schema format. It's a
straight-forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/fpga/lattice,ice40-fpga-mgr.yaml | 59 +++++++++++++++++++
.../bindings/fpga/lattice-ice40-fpga-mgr.txt | 21 -------
2 files changed, 59 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ice40-fpga-mgr.yaml
delete mode 100644 Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
diff --git a/Documentation/devicetree/bindings/fpga/lattice,ice40-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ice40-fpga-mgr.yaml
new file mode 100644
index 000000000000..5121c6120785
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/lattice,ice40-fpga-mgr.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/lattice,ice40-fpga-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lattice iCE40 FPGA Manager
+
+maintainers:
+ - Joel Holdsworth <joel@airwebreathe.org.uk>
+
+properties:
+ compatible:
+ const: lattice,ice40-fpga-mgr
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ minimum: 1000000
+ maximum: 25000000
+
+ cdone-gpios:
+ maxItems: 1
+ description: GPIO input connected to CDONE pin
+
+ reset-gpios:
+ maxItems: 1
+ description:
+ Active-low GPIO output connected to CRESET_B pin. Note that unless the
+ GPIO is held low during startup, the FPGA will enter Master SPI mode and
+ drive SCK with a clock signal potentially jamming other devices on the bus
+ until the firmware is loaded.
+
+required:
+ - compatible
+ - reg
+ - spi-max-frequency
+ - cdone-gpios
+ - reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga@0 {
+ compatible = "lattice,ice40-fpga-mgr";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
deleted file mode 100644
index 4dc412437b08..000000000000
--- a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Lattice iCE40 FPGA Manager
-
-Required properties:
-- compatible: Should contain "lattice,ice40-fpga-mgr"
-- reg: SPI chip select
-- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
-- cdone-gpios: GPIO input connected to CDONE pin
-- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
- that unless the GPIO is held low during startup, the
- FPGA will enter Master SPI mode and drive SCK with a
- clock signal potentially jamming other devices on the
- bus until the firmware is loaded.
-
-Example:
- fpga: fpga@0 {
- compatible = "lattice,ice40-fpga-mgr";
- reg = <0>;
- spi-max-frequency = <1000000>;
- cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
- };
--
2.51.0
On Wed, Oct 29, 2025 at 01:55:01PM -0500, Rob Herring (Arm) wrote: > + > +title: Lattice iCE40 FPGA Manager > + > +maintainers: > + - Joel Holdsworth <joel@airwebreathe.org.uk> > + You miss spi-peripheral-props > +properties: > + compatible: > + const: lattice,ice40-fpga-mgr > + > + reg: > + maxItems: 1 > + > + spi-max-frequency: > + minimum: 1000000 > + maximum: 25000000 > + > + cdone-gpios: > + maxItems: 1 > + description: GPIO input connected to CDONE pin > + > + reset-gpios: > + maxItems: 1 > + description: > + Active-low GPIO output connected to CRESET_B pin. Note that unless the > + GPIO is held low during startup, the FPGA will enter Master SPI mode and > + drive SCK with a clock signal potentially jamming other devices on the bus > + until the firmware is loaded. > + > +required: > + - compatible > + - reg > + - spi-max-frequency > + - cdone-gpios > + - reset-gpios > + > +additionalProperties: false ... and here unevaluatedProperties. Best regards, Krzysztof
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