From: Rohan G Thomas <rohan.g.thomas@altera.com>

Agilex5 HPS EMAC uses the dwxgmac-3.10a IP, unlike previous socfpga
platforms which use dwmac1000 IP. Due to differences in platform
configuration, Agilex5 requires a distinct setup.

Introduce a setup_plat_dat() callback in socfpga_dwmac_ops to handle
platform-specific setup. This callback is invoked before
stmmac_dvr_probe() to ensure the platform data is correctly
configured. Also, implemented separate setup_plat_dat() callback for
current socfpga platforms and Agilex5.

Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
---
 .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c    | 53 ++++++++++++++++++----
 1 file changed, 43 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 2ff5db6d41ca08a1652d57f3eb73923b9a9558bf..3dae4f3c103802ed1c2cd390634bd5473192d4ee 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -44,6 +44,7 @@
 struct socfpga_dwmac;
 struct socfpga_dwmac_ops {
 	int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
+	void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv);
 };
 
 struct socfpga_dwmac {
@@ -441,6 +442,39 @@ static int socfpga_dwmac_init(struct platform_device *pdev, void *bsp_priv)
 	return dwmac->ops->set_phy_mode(dwmac);
 }
 
+static void socfpga_common_plat_dat(struct socfpga_dwmac *dwmac)
+{
+	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
+
+	plat_dat->bsp_priv = dwmac;
+	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
+	plat_dat->init = socfpga_dwmac_init;
+	plat_dat->pcs_init = socfpga_dwmac_pcs_init;
+	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
+	plat_dat->select_pcs = socfpga_dwmac_select_pcs;
+}
+
+static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
+{
+	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
+
+	socfpga_common_plat_dat(dwmac);
+
+	plat_dat->core_type = DWMAC_CORE_GMAC;
+
+	/* Rx watchdog timer in dwmac is buggy in this hw */
+	plat_dat->riwt_off = 1;
+}
+
+static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
+{
+	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
+
+	socfpga_common_plat_dat(dwmac);
+
+	plat_dat->core_type = DWMAC_CORE_XGMAC;
+}
+
 static int socfpga_dwmac_probe(struct platform_device *pdev)
 {
 	struct plat_stmmacenet_data *plat_dat;
@@ -491,31 +525,30 @@ static int socfpga_dwmac_probe(struct platform_device *pdev)
 	dwmac->ops = ops;
 	dwmac->plat_dat = plat_dat;
 
-	plat_dat->bsp_priv = dwmac;
-	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
-	plat_dat->init = socfpga_dwmac_init;
-	plat_dat->pcs_init = socfpga_dwmac_pcs_init;
-	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
-	plat_dat->select_pcs = socfpga_dwmac_select_pcs;
-	plat_dat->core_type = DWMAC_CORE_GMAC;
-
-	plat_dat->riwt_off = 1;
+	ops->setup_plat_dat(dwmac);
 
 	return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
 }
 
 static const struct socfpga_dwmac_ops socfpga_gen5_ops = {
 	.set_phy_mode = socfpga_gen5_set_phy_mode,
+	.setup_plat_dat = socfpga_gen5_setup_plat_dat,
 };
 
 static const struct socfpga_dwmac_ops socfpga_gen10_ops = {
 	.set_phy_mode = socfpga_gen10_set_phy_mode,
+	.setup_plat_dat = socfpga_gen5_setup_plat_dat,
+};
+
+static const struct socfpga_dwmac_ops socfpga_agilex5_ops = {
+	.set_phy_mode = socfpga_gen10_set_phy_mode,
+	.setup_plat_dat = socfpga_agilex5_setup_plat_dat,
 };
 
 static const struct of_device_id socfpga_dwmac_match[] = {
 	{ .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
 	{ .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
-	{ .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_gen10_ops },
+	{ .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_agilex5_ops },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);

-- 
2.43.7

On Wed, Oct 29, 2025 at 04:06:13PM +0800, Rohan G Thomas via B4 Relay wrote:
> +static void socfpga_common_plat_dat(struct socfpga_dwmac *dwmac)
> +{
> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
> +
> +	plat_dat->bsp_priv = dwmac;

Surely this is something which is always done? What's the point in
moving this to a function that always needs to be called from the
implementation specific setup_plat_dat() method?

> +	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
> +	plat_dat->init = socfpga_dwmac_init;
> +	plat_dat->pcs_init = socfpga_dwmac_pcs_init;
> +	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
> +	plat_dat->select_pcs = socfpga_dwmac_select_pcs;

From what I can see in your patch series, these are never changed.
So, I question the value of having this "common_plat_dat"
initialisation function. Why not leave this code in
socfpga_dwmac_probe(), and just move the initialisation of
plat_dat->core_type and plat_dat->riwt_off ?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Hi Russell,

Thanks for reviewing the patch.

On 10/29/2025 9:44 PM, Russell King (Oracle) wrote:
> On Wed, Oct 29, 2025 at 04:06:13PM +0800, Rohan G Thomas via B4 Relay wrote:
>> +static void socfpga_common_plat_dat(struct socfpga_dwmac *dwmac)
>> +{
>> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
>> +
>> +	plat_dat->bsp_priv = dwmac;
> 
> Surely this is something which is always done? What's the point in
> moving this to a function that always needs to be called from the
> implementation specific setup_plat_dat() method?
> 

Yes, for all the current platforms this is common.

>> +	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
>> +	plat_dat->init = socfpga_dwmac_init;
>> +	plat_dat->pcs_init = socfpga_dwmac_pcs_init;
>> +	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
>> +	plat_dat->select_pcs = socfpga_dwmac_select_pcs;
> 
>  From what I can see in your patch series, these are never changed.
> So, I question the value of having this "common_plat_dat"
> initialisation function. Why not leave this code in
> socfpga_dwmac_probe(), and just move the initialisation of
> plat_dat->core_type and plat_dat->riwt_off ?
> 

Agreed. Will keep it in socfpga_dwmac_probe() itself.

Best Regards,
Rohan

Hi Rohan,

As this patch also impacts other socfpga variants, I gave it a try
on Cyclone V, all is fine :)

On 29/10/2025 09:06, Rohan G Thomas via B4 Relay wrote:
> From: Rohan G Thomas <rohan.g.thomas@altera.com>
> 
> Agilex5 HPS EMAC uses the dwxgmac-3.10a IP, unlike previous socfpga
> platforms which use dwmac1000 IP. Due to differences in platform
> configuration, Agilex5 requires a distinct setup.
> 
> Introduce a setup_plat_dat() callback in socfpga_dwmac_ops to handle
> platform-specific setup. This callback is invoked before
> stmmac_dvr_probe() to ensure the platform data is correctly
> configured. Also, implemented separate setup_plat_dat() callback for
> current socfpga platforms and Agilex5.
> 
> Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>

Thanks for your explanation about the TSE PCS,

Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com>

Maxime

Hi Rohan,

On 29/10/2025 09:06, Rohan G Thomas via B4 Relay wrote:
> From: Rohan G Thomas <rohan.g.thomas@altera.com>
> 
> Agilex5 HPS EMAC uses the dwxgmac-3.10a IP, unlike previous socfpga
> platforms which use dwmac1000 IP. Due to differences in platform
> configuration, Agilex5 requires a distinct setup.
> 
> Introduce a setup_plat_dat() callback in socfpga_dwmac_ops to handle
> platform-specific setup. This callback is invoked before
> stmmac_dvr_probe() to ensure the platform data is correctly
> configured. Also, implemented separate setup_plat_dat() callback for
> current socfpga platforms and Agilex5.
> 
> Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
> ---
>  .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c    | 53 ++++++++++++++++++----
>  1 file changed, 43 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> index 2ff5db6d41ca08a1652d57f3eb73923b9a9558bf..3dae4f3c103802ed1c2cd390634bd5473192d4ee 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> @@ -44,6 +44,7 @@
>  struct socfpga_dwmac;
>  struct socfpga_dwmac_ops {
>  	int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
> +	void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv);
>  };
>  
>  struct socfpga_dwmac {
> @@ -441,6 +442,39 @@ static int socfpga_dwmac_init(struct platform_device *pdev, void *bsp_priv)
>  	return dwmac->ops->set_phy_mode(dwmac);
>  }
>  
> +static void socfpga_common_plat_dat(struct socfpga_dwmac *dwmac)
> +{
> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
> +
> +	plat_dat->bsp_priv = dwmac;
> +	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
> +	plat_dat->init = socfpga_dwmac_init;
> +	plat_dat->pcs_init = socfpga_dwmac_pcs_init;
> +	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
> +	plat_dat->select_pcs = socfpga_dwmac_select_pcs;
> +}
> +
> +static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
> +{
> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
> +
> +	socfpga_common_plat_dat(dwmac);
> +
> +	plat_dat->core_type = DWMAC_CORE_GMAC;
> +
> +	/* Rx watchdog timer in dwmac is buggy in this hw */
> +	plat_dat->riwt_off = 1;
> +}
> +
> +static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
> +{
> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
> +
> +	socfpga_common_plat_dat(dwmac);

I"m not familiar with this device (I only have a Cyclone V on hand), does
it still make sense to try to instantiate a Lynx (i.e. Altera TSE) PCS
for that IP ?

Maxime

Hi Maxime,

On 10/29/2025 7:04 PM, Maxime Chevallier wrote:
> Hi Rohan,
> 
> On 29/10/2025 09:06, Rohan G Thomas via B4 Relay wrote:
>> From: Rohan G Thomas <rohan.g.thomas@altera.com>
>>
>> Agilex5 HPS EMAC uses the dwxgmac-3.10a IP, unlike previous socfpga
>> platforms which use dwmac1000 IP. Due to differences in platform
>> configuration, Agilex5 requires a distinct setup.
>>
>> Introduce a setup_plat_dat() callback in socfpga_dwmac_ops to handle
>> platform-specific setup. This callback is invoked before
>> stmmac_dvr_probe() to ensure the platform data is correctly
>> configured. Also, implemented separate setup_plat_dat() callback for
>> current socfpga platforms and Agilex5.
>>
>> Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
>> ---
>>   .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c    | 53 ++++++++++++++++++----
>>   1 file changed, 43 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
>> index 2ff5db6d41ca08a1652d57f3eb73923b9a9558bf..3dae4f3c103802ed1c2cd390634bd5473192d4ee 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
>> @@ -44,6 +44,7 @@
>>   struct socfpga_dwmac;
>>   struct socfpga_dwmac_ops {
>>   	int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
>> +	void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv);
>>   };
>>   
>>   struct socfpga_dwmac {
>> @@ -441,6 +442,39 @@ static int socfpga_dwmac_init(struct platform_device *pdev, void *bsp_priv)
>>   	return dwmac->ops->set_phy_mode(dwmac);
>>   }
>>   
>> +static void socfpga_common_plat_dat(struct socfpga_dwmac *dwmac)
>> +{
>> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
>> +
>> +	plat_dat->bsp_priv = dwmac;
>> +	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
>> +	plat_dat->init = socfpga_dwmac_init;
>> +	plat_dat->pcs_init = socfpga_dwmac_pcs_init;
>> +	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
>> +	plat_dat->select_pcs = socfpga_dwmac_select_pcs;
>> +}
>> +
>> +static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
>> +{
>> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
>> +
>> +	socfpga_common_plat_dat(dwmac);
>> +
>> +	plat_dat->core_type = DWMAC_CORE_GMAC;
>> +
>> +	/* Rx watchdog timer in dwmac is buggy in this hw */
>> +	plat_dat->riwt_off = 1;
>> +}
>> +
>> +static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
>> +{
>> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
>> +
>> +	socfpga_common_plat_dat(dwmac);
> 
> I"m not familiar with this device (I only have a Cyclone V on hand), does
> it still make sense to try to instantiate a Lynx (i.e. Altera TSE) PCS
> for that IP ?

AFAIK, yes it is supported by Agilex V device family also.
https://www.altera.com/products/ip/a1jui0000049uuomam/triple-speed-ethernet-fpga-ip

> 
> Maxime
> 

Best Regards,
Rohan

Hi,

On 29/10/2025 15:53, G Thomas, Rohan wrote:
> Hi Maxime,
> 
> On 10/29/2025 7:04 PM, Maxime Chevallier wrote:
>> Hi Rohan,
>>
>> On 29/10/2025 09:06, Rohan G Thomas via B4 Relay wrote:
>>> From: Rohan G Thomas <rohan.g.thomas@altera.com>
>>>
>>> Agilex5 HPS EMAC uses the dwxgmac-3.10a IP, unlike previous socfpga
>>> platforms which use dwmac1000 IP. Due to differences in platform
>>> configuration, Agilex5 requires a distinct setup.
>>>
>>> Introduce a setup_plat_dat() callback in socfpga_dwmac_ops to handle
>>> platform-specific setup. This callback is invoked before
>>> stmmac_dvr_probe() to ensure the platform data is correctly
>>> configured. Also, implemented separate setup_plat_dat() callback for
>>> current socfpga platforms and Agilex5.
>>>
>>> Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
>>> ---
>>>   .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c    | 53 ++++++++++++++++++----
>>>   1 file changed, 43 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
>>> index 2ff5db6d41ca08a1652d57f3eb73923b9a9558bf..3dae4f3c103802ed1c2cd390634bd5473192d4ee 100644
>>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
>>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
>>> @@ -44,6 +44,7 @@
>>>   struct socfpga_dwmac;
>>>   struct socfpga_dwmac_ops {
>>>   	int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
>>> +	void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv);
>>>   };
>>>   
>>>   struct socfpga_dwmac {
>>> @@ -441,6 +442,39 @@ static int socfpga_dwmac_init(struct platform_device *pdev, void *bsp_priv)
>>>   	return dwmac->ops->set_phy_mode(dwmac);
>>>   }
>>>   
>>> +static void socfpga_common_plat_dat(struct socfpga_dwmac *dwmac)
>>> +{
>>> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
>>> +
>>> +	plat_dat->bsp_priv = dwmac;
>>> +	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
>>> +	plat_dat->init = socfpga_dwmac_init;
>>> +	plat_dat->pcs_init = socfpga_dwmac_pcs_init;
>>> +	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
>>> +	plat_dat->select_pcs = socfpga_dwmac_select_pcs;
>>> +}
>>> +
>>> +static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
>>> +{
>>> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
>>> +
>>> +	socfpga_common_plat_dat(dwmac);
>>> +
>>> +	plat_dat->core_type = DWMAC_CORE_GMAC;
>>> +
>>> +	/* Rx watchdog timer in dwmac is buggy in this hw */
>>> +	plat_dat->riwt_off = 1;
>>> +}
>>> +
>>> +static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
>>> +{
>>> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
>>> +
>>> +	socfpga_common_plat_dat(dwmac);
>>
>> I"m not familiar with this device (I only have a Cyclone V on hand), does
>> it still make sense to try to instantiate a Lynx (i.e. Altera TSE) PCS
>> for that IP ?
> 
> AFAIK, yes it is supported by Agilex V device family also.
> https://www.altera.com/products/ip/a1jui0000049uuomam/triple-speed-ethernet-fpga-ip

Ah nice to know, thanks !

this looks correct then :)

Maxime

> 
>>
>> Maxime
>>
> 
> Best Regards,
> Rohan
>