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[PATCH 2/6] arm64: dts: agilex5: Add ECC manager and submodule nodes

niravkumarlaxmidas.rabara@altera.com posted 6 patches 3 months, 2 weeks ago
[PATCH 2/6] arm64: dts: agilex5: Add ECC manager and submodule nodes
Posted by niravkumarlaxmidas.rabara@altera.com 3 months, 2 weeks ago 
From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>

Add the ECC manager (eccmgr) node and its associated ECC submodules to the
Agilex5 SoCFPGA device tree. The eccmgr node serves as a logical parent to
group various ECC hardware instances, including those for USB, Ethernet,
OCRAM, IO96B memory controllers, Secure Device Manager (SDM) QSPI, and
Configuration RAM (CRAM) Single Event Upset (SEU) subsystems.

Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 98 +++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 04e99cd7e74b..5ea7a506d3d2 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -428,6 +428,104 @@ usb0: usb@10b00000 {
 			status = "disabled";
 		};
 
+		eccmgr {
+			compatible = "altr,socfpga-a10-ecc-manager";
+			altr,sysmgr-syscon = <&sysmgr>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global_sbe", "global_dbe", "io96b0" , "io96b1",
+					  "sdm_qspi_sbe", "sdm_qspi_dbe", "sdm_seu";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			ranges;
+
+			ocram-ecc@108cc000 {
+				compatible = "altr,socfpga-a10-ocram-ecc";
+				reg = <0x108cc000 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, <33 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			usb0-ecc@108c4000 {
+				compatible = "altr,socfpga-usb-ecc";
+				reg = <0x108c4000 0x100>;
+				altr,ecc-parent = <&usb0>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, <34 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			emac0-rx-ecc@108c0000 {
+				compatible = "altr,socfpga-eth-mac-ecc";
+				reg = <0x108c0000 0x100>;
+				altr,ecc-parent = <&gmac0>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, <38 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			emac0-tx-ecc@108c0400 {
+				compatible = "altr,socfpga-eth-mac-ecc";
+				reg = <0x108c0400 0x100>;
+				altr,ecc-parent = <&gmac0>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, <37 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			emac1-rx-ecc@108c0800 {
+				compatible = "altr,socfpga-eth-mac-ecc";
+				reg = <0x108c0800 0x100>;
+				altr,ecc-parent = <&gmac1>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, <38 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			emac1-tx-ecc@108c0c00 {
+				compatible = "altr,socfpga-eth-mac-ecc";
+				reg = <0x108c0c00 0x100>;
+				altr,ecc-parent = <&gmac1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <39 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			emac2-rx-ecc@108c1000 {
+				compatible = "altr,socfpga-eth-mac-ecc";
+				reg = <0x108c1000 0x100>;
+				altr,ecc-parent = <&gmac2>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, <40 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			emac2-tx-ecc@108c1400 {
+				compatible = "altr,socfpga-eth-mac-ecc";
+				reg = <0x108c1400 0x100>;
+				altr,ecc-parent = <&gmac2>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>, <41 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			io96b0-ecc@18400000 {
+				compatible = "altr,socfpga-io96b0-ecc";
+				reg = <0x18400000 0x1000>;
+			};
+
+			io96b1-ecc@18800000 {
+				compatible = "altr,socfpga-io96b1-ecc";
+				reg = <0x18800000 0x1000>;
+				status = "disabled";
+			};
+
+			sdm-qspi-ecc@10a22000 {
+				compatible = "altr,socfpga-sdm-qspi-ecc";
+				reg = <0x10a22000 0x100>;
+			};
+
+			cram-seu {
+				compatible = "altr,socfpga-cram-seu";
+				altr,seu-safe-inject-ce-msb = <0x0>;
+				altr,seu-safe-inject-ce-lsb = <0x30000>;
+				altr,seu-safe-inject-ue-msb = <0x20>;
+				altr,seu-safe-inject-ue-lsb = <0x30001>;
+			};
+		};
+
 		watchdog0: watchdog@10d00200 {
 			compatible = "snps,dw-wdt";
 			reg = <0x10d00200 0x100>;
-- 
2.25.1
Re: [PATCH 2/6] arm64: dts: agilex5: Add ECC manager and submodule nodes
Posted by Krzysztof Kozlowski 3 months, 1 week ago 
On Tue, Oct 28, 2025 at 05:22:28PM +0800, niravkumarlaxmidas.rabara@altera.com wrote:
> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
> 
> Add the ECC manager (eccmgr) node and its associated ECC submodules to the
> Agilex5 SoCFPGA device tree. The eccmgr node serves as a logical parent to
> group various ECC hardware instances, including those for USB, Ethernet,
> OCRAM, IO96B memory controllers, Secure Device Manager (SDM) QSPI, and
> Configuration RAM (CRAM) Single Event Upset (SEU) subsystems.
> 
> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
> ---
>  .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 98 +++++++++++++++++++
>  1 file changed, 98 insertions(+)

DTS cannot be the second patch. Organize your patchset correctly, see
submitting patches.


> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 04e99cd7e74b..5ea7a506d3d2 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -428,6 +428,104 @@ usb0: usb@10b00000 {
>  			status = "disabled";
>  		};
>  
> +		eccmgr {
> +			compatible = "altr,socfpga-a10-ecc-manager";
> +			altr,sysmgr-syscon = <&sysmgr>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "global_sbe", "global_dbe", "io96b0" , "io96b1",
> +					  "sdm_qspi_sbe", "sdm_qspi_dbe", "sdm_seu";
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			ranges;
> +
> +			ocram-ecc@108cc000 {
> +				compatible = "altr,socfpga-a10-ocram-ecc";
> +				reg = <0x108cc000 0x100>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, <33 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			usb0-ecc@108c4000 {
> +				compatible = "altr,socfpga-usb-ecc";
> +				reg = <0x108c4000 0x100>;
> +				altr,ecc-parent = <&usb0>;
> +				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, <34 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac0-rx-ecc@108c0000 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c0000 0x100>;
> +				altr,ecc-parent = <&gmac0>;
> +				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, <38 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac0-tx-ecc@108c0400 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c0400 0x100>;
> +				altr,ecc-parent = <&gmac0>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, <37 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac1-rx-ecc@108c0800 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c0800 0x100>;
> +				altr,ecc-parent = <&gmac1>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, <38 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac1-tx-ecc@108c0c00 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c0c00 0x100>;
> +				altr,ecc-parent = <&gmac1>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <39 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac2-rx-ecc@108c1000 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c1000 0x100>;
> +				altr,ecc-parent = <&gmac2>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, <40 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac2-tx-ecc@108c1400 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c1400 0x100>;
> +				altr,ecc-parent = <&gmac2>;
> +				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>, <41 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			io96b0-ecc@18400000 {
> +				compatible = "altr,socfpga-io96b0-ecc";
> +				reg = <0x18400000 0x1000>;

Could not express more: NAK. Completely pointless node with pointless
name.

Best regards,
Krzysztof

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