From: Tao Zhang <tao.zhang@oss.qualcomm.com>
Introduce sysfs nodes to configure cross-trigger parameters for TPDA.
These registers define the characteristics of cross-trigger packets,
including generation frequency and flag values.
Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
.../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 ++++
drivers/hwtracing/coresight/coresight-tpda.c | 230 +++++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpda.h | 27 ++-
3 files changed, 299 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
new file mode 100644
index 000000000000..80e4b05a1ab4
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
@@ -0,0 +1,43 @@
+What: /sys/bus/coresight/devices/<tpda-name>/trig_async_enable
+Date: October 2025
+KernelVersion: 6.19
+Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
+Description:
+ (RW) Enable/disable cross trigger synchronization sequence interface.
+
+What: /sys/bus/coresight/devices/<tpda-name>/trig_flag_ts_enable
+Date: October 2025
+KernelVersion: 6.19
+Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
+Description:
+ (RW) Enable/disable cross trigger FLAG packet request interface.
+
+What: /sys/bus/coresight/devices/<tpda-name>/trig_freq_enable
+Date: October 2025
+KernelVersion: 6.19
+Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
+Description:
+ (RW) Enable/disable cross trigger FREQ packet request interface.
+
+What: /sys/bus/coresight/devices/<tpda-name>/freq_ts_enable
+Date: October 2025
+KernelVersion: 6.19
+Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
+Description:
+ (RW) Enable/disable the timestamp for all FREQ packets.
+
+What: /sys/bus/coresight/devices/<tpda-name>/global_flush_req
+Date: October 2025
+KernelVersion: 6.19
+Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
+Description:
+ (RW) Set global (all ports) flush request bit. The bit remains set until a
+ global flush request sequence completes.
+
+What: /sys/bus/coresight/devices/<tpda-name>/cmbchan_mode
+Date: October 2025
+KernelVersion: 6.19
+Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
+Description:
+ (RW) Configure the CMB/MCMB channel mode for all enabled ports.
+ Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode.
diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c
index 333b3cb23685..a9a27bcc65a1 100644
--- a/drivers/hwtracing/coresight/coresight-tpda.c
+++ b/drivers/hwtracing/coresight/coresight-tpda.c
@@ -147,9 +147,37 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)
u32 val;
val = readl_relaxed(drvdata->base + TPDA_CR);
+ val &= ~TPDA_CR_MID;
val &= ~TPDA_CR_ATID;
val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid);
+ if (drvdata->trig_async)
+ val |= TPDA_CR_SRIE;
+ else
+ val &= ~TPDA_CR_SRIE;
+ if (drvdata->trig_flag_ts)
+ val |= TPDA_CR_FLRIE;
+ else
+ val &= ~TPDA_CR_FLRIE;
+ if (drvdata->trig_freq)
+ val |= TPDA_CR_FRIE;
+ else
+ val &= ~TPDA_CR_FRIE;
+ if (drvdata->freq_ts)
+ val |= TPDA_CR_FREQTS;
+ else
+ val &= ~TPDA_CR_FREQTS;
+ if (drvdata->cmbchan_mode)
+ val |= TPDA_CR_CMBCHANMODE;
+ else
+ val &= ~TPDA_CR_CMBCHANMODE;
writel_relaxed(val, drvdata->base + TPDA_CR);
+
+ /*
+ * If FLRIE bit is set, set the master and channel
+ * id as zero
+ */
+ if (drvdata->trig_flag_ts)
+ writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR);
}
static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)
@@ -265,6 +293,206 @@ static const struct coresight_ops tpda_cs_ops = {
.link_ops = &tpda_link_ops,
};
+static ssize_t trig_async_enable_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async);
+}
+
+static ssize_t trig_async_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (kstrtoul(buf, 0, &val))
+ return -EINVAL;
+
+ guard(spinlock)(&drvdata->spinlock);
+ drvdata->trig_async = !!val;
+
+ return size;
+}
+static DEVICE_ATTR_RW(trig_async_enable);
+
+static ssize_t trig_flag_ts_enable_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts);
+}
+
+static ssize_t trig_flag_ts_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (kstrtoul(buf, 0, &val))
+ return -EINVAL;
+
+ guard(spinlock)(&drvdata->spinlock);
+ drvdata->trig_flag_ts = !!val;
+
+ return size;
+}
+static DEVICE_ATTR_RW(trig_flag_ts_enable);
+
+static ssize_t trig_freq_enable_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq);
+}
+
+static ssize_t trig_freq_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (kstrtoul(buf, 0, &val))
+ return -EINVAL;
+
+ guard(spinlock)(&drvdata->spinlock);
+ drvdata->trig_freq = !!val;
+
+ return size;
+}
+static DEVICE_ATTR_RW(trig_freq_enable);
+
+static ssize_t freq_ts_enable_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts);
+}
+
+static ssize_t freq_ts_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (kstrtoul(buf, 0, &val))
+ return -EINVAL;
+
+ guard(spinlock)(&drvdata->spinlock);
+ drvdata->freq_ts = !!val;
+
+ return size;
+}
+static DEVICE_ATTR_RW(freq_ts_enable);
+
+static ssize_t global_flush_req_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (!drvdata->csdev->refcnt)
+ return -EINVAL;
+
+ guard(spinlock)(&drvdata->spinlock);
+ CS_UNLOCK(drvdata->base);
+ val = readl_relaxed(drvdata->base + TPDA_CR);
+ CS_LOCK(drvdata->base);
+ /* Only read value for bit 0 */
+ val &= BIT(0);
+
+ return sysfs_emit(buf, "%lu\n", val);
+}
+
+static ssize_t global_flush_req_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (kstrtoul(buf, 0, &val))
+ return -EINVAL;
+
+ if (!drvdata->csdev->refcnt || !val)
+ return -EINVAL;
+
+ guard(spinlock)(&drvdata->spinlock);
+ CS_UNLOCK(drvdata->base);
+ val = readl_relaxed(drvdata->base + TPDA_CR);
+ /* Only set bit 0 */
+ val |= BIT(0);
+ writel_relaxed(val, drvdata->base + TPDA_CR);
+ CS_LOCK(drvdata->base);
+
+ return size;
+}
+static DEVICE_ATTR_RW(global_flush_req);
+
+static ssize_t cmbchan_mode_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode);
+}
+
+static ssize_t cmbchan_mode_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ if (kstrtoul(buf, 0, &val))
+ return -EINVAL;
+
+ guard(spinlock)(&drvdata->spinlock);
+ drvdata->cmbchan_mode = !!val;
+
+ return size;
+}
+static DEVICE_ATTR_RW(cmbchan_mode);
+
+static struct attribute *tpda_attrs[] = {
+ &dev_attr_trig_async_enable.attr,
+ &dev_attr_trig_flag_ts_enable.attr,
+ &dev_attr_trig_freq_enable.attr,
+ &dev_attr_freq_ts_enable.attr,
+ &dev_attr_global_flush_req.attr,
+ &dev_attr_cmbchan_mode.attr,
+ NULL,
+};
+
+static struct attribute_group tpda_attr_grp = {
+ .attrs = tpda_attrs,
+};
+
+static const struct attribute_group *tpda_attr_grps[] = {
+ &tpda_attr_grp,
+ NULL,
+};
+
static int tpda_init_default_data(struct tpda_drvdata *drvdata)
{
int atid;
@@ -280,6 +508,7 @@ static int tpda_init_default_data(struct tpda_drvdata *drvdata)
return atid;
drvdata->atid = atid;
+ drvdata->freq_ts = true;
return 0;
}
@@ -323,6 +552,7 @@ static int tpda_probe(struct amba_device *adev, const struct amba_id *id)
desc.ops = &tpda_cs_ops;
desc.pdata = adev->dev.platform_data;
desc.dev = &adev->dev;
+ desc.groups = tpda_attr_grps;
desc.access = CSDEV_ACCESS_IOMEM(base);
drvdata->csdev = coresight_register(&desc);
if (IS_ERR(drvdata->csdev))
diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h
index c6af3d2da3ef..0be625fb52fd 100644
--- a/drivers/hwtracing/coresight/coresight-tpda.h
+++ b/drivers/hwtracing/coresight/coresight-tpda.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CORESIGHT_CORESIGHT_TPDA_H
@@ -8,6 +8,19 @@
#define TPDA_CR (0x000)
#define TPDA_Pn_CR(n) (0x004 + (n * 4))
+#define TPDA_FPID_CR (0x084)
+
+/* Cross trigger FREQ packets timestamp bit */
+#define TPDA_CR_FREQTS BIT(2)
+/* Cross trigger FREQ packet request bit */
+#define TPDA_CR_FRIE BIT(3)
+/* Cross trigger FLAG packet request interface bit */
+#define TPDA_CR_FLRIE BIT(4)
+/* Cross trigger synchronization bit */
+#define TPDA_CR_SRIE BIT(5)
+/* Packetize CMB/MCMB traffic bit */
+#define TPDA_CR_CMBCHANMODE BIT(20)
+
/* Aggregator port enable bit */
#define TPDA_Pn_CR_ENA BIT(0)
/* Aggregator port CMB data set element size bit */
@@ -19,6 +32,8 @@
/* Bits 6 ~ 12 is for atid value */
#define TPDA_CR_ATID GENMASK(12, 6)
+/* Bits 13 ~ 19 is for mid value */
+#define TPDA_CR_MID GENMASK(19, 13)
/**
* struct tpda_drvdata - specifics associated to an TPDA component
@@ -29,6 +44,11 @@
* @enable: enable status of the component.
* @dsb_esize Record the DSB element size.
* @cmb_esize Record the CMB element size.
+ * @trig_async: Enable/disable cross trigger synchronization sequence interface.
+ * @trig_flag_ts: Enable/disable cross trigger FLAG packet request interface.
+ * @trig_freq: Enable/disable cross trigger FREQ packet request interface.
+ * @freq_ts: Enable/disable the timestamp for all FREQ packets.
+ * @cmbchan_mode: Configure the CMB/MCMB channel mode.
*/
struct tpda_drvdata {
void __iomem *base;
@@ -38,6 +58,11 @@ struct tpda_drvdata {
u8 atid;
u32 dsb_esize;
u32 cmb_esize;
+ bool trig_async;
+ bool trig_flag_ts;
+ bool trig_freq;
+ bool freq_ts;
+ bool cmbchan_mode;
};
#endif /* _CORESIGHT_CORESIGHT_TPDA_H */
--
2.34.1On 28/10/2025 02:02, Jie Gan wrote:
> From: Tao Zhang <tao.zhang@oss.qualcomm.com>
>
> Introduce sysfs nodes to configure cross-trigger parameters for TPDA.
> These registers define the characteristics of cross-trigger packets,
> including generation frequency and flag values.
>
> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com>
> Reviewed-by: James Clark <james.clark@linaro.org>
> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 ++++
> drivers/hwtracing/coresight/coresight-tpda.c | 230 +++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpda.h | 27 ++-
> 3 files changed, 299 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
> new file mode 100644
> index 000000000000..80e4b05a1ab4
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
> @@ -0,0 +1,43 @@
> +What: /sys/bus/coresight/devices/<tpda-name>/trig_async_enable
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Enable/disable cross trigger synchronization sequence interface.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/trig_flag_ts_enable
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Enable/disable cross trigger FLAG packet request interface.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/trig_freq_enable
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Enable/disable cross trigger FREQ packet request interface.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/freq_ts_enable
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Enable/disable the timestamp for all FREQ packets.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/global_flush_req
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Set global (all ports) flush request bit. The bit remains set until a
> + global flush request sequence completes.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/cmbchan_mode
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Configure the CMB/MCMB channel mode for all enabled ports.
> + Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode.
> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c
> index 333b3cb23685..a9a27bcc65a1 100644
> --- a/drivers/hwtracing/coresight/coresight-tpda.c
> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
> @@ -147,9 +147,37 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)
> u32 val;
>
> val = readl_relaxed(drvdata->base + TPDA_CR);
> + val &= ~TPDA_CR_MID;
> val &= ~TPDA_CR_ATID;
See, below.
> val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid);
> + if (drvdata->trig_async)
> + val |= TPDA_CR_SRIE;
> + else
> + val &= ~TPDA_CR_SRIE;
> + if (drvdata->trig_flag_ts)
> + val |= TPDA_CR_FLRIE;
> + else
> + val &= ~TPDA_CR_FLRIE;
> + if (drvdata->trig_freq)
> + val |= TPDA_CR_FRIE;
> + else
> + val &= ~TPDA_CR_FRIE;
> + if (drvdata->freq_ts)
> + val |= TPDA_CR_FREQTS;
> + else
> + val &= ~TPDA_CR_FREQTS;
> + if (drvdata->cmbchan_mode)
> + val |= TPDA_CR_CMBCHANMODE;
> + else
> + val &= ~TPDA_CR_CMBCHANMODE;
Could we clear all of the bits that are configurable in one go in the
beginning and set the appropriate ones based on the setting ? i.e.:
Do we really need to retain any values ? And if not, why not start
with a fresh set of values and avoid the read ?
> writel_relaxed(val, drvdata->base + TPDA_CR);
> +
> + /*
> + * If FLRIE bit is set, set the master and channel
> + * id as zero
> + */
> + if (drvdata->trig_flag_ts)
> + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR);
> }
>
> static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)
> @@ -265,6 +293,206 @@ static const struct coresight_ops tpda_cs_ops = {
> .link_ops = &tpda_link_ops,
> };
>
> +static ssize_t trig_async_enable_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async);
> +}
> +
> +static ssize_t trig_async_enable_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + drvdata->trig_async = !!val;
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(trig_async_enable);
...
> +static DEVICE_ATTR_RW(trig_flag_ts_enable);
...
> +static DEVICE_ATTR_RW(trig_freq_enable);
...
> +static DEVICE_ATTR_RW(freq_ts_enable);
These attribute are boolean and looks like we could save some space on
code by using dev_ext_attribute.
see tpdm_simple_dataset_rw()/tpdm_simple_dataset_ro() . You could
#define TPDA_TRIG_ASYNC 0
#define TPDA_TRIG_FLAG_TS 1
#define TPDA_TRIG_FREQ 2
tpda_trig_sysfs_show/store()
bool *ptr;
switch (eattr->var) {
case TPDA_TRIG_ASYNC:
ptr = &drvdata->trig_async;
break;
case TPDA_TRIG_FLAG_TS:
ptr = &drvdata->trig_flag_ts;
break;
...
}
> +
> +static ssize_t global_flush_req_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (!drvdata->csdev->refcnt)
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + CS_UNLOCK(drvdata->base);
> + val = readl_relaxed(drvdata->base + TPDA_CR);
> + CS_LOCK(drvdata->base);
> + /* Only read value for bit 0 */
> + val &= BIT(0);
> +
> + return sysfs_emit(buf, "%lu\n", val);
> +}
> +
> +static ssize_t global_flush_req_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + if (!drvdata->csdev->refcnt || !val)
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + CS_UNLOCK(drvdata->base);
> + val = readl_relaxed(drvdata->base + TPDA_CR);
> + /* Only set bit 0 */
> + val |= BIT(0);
What is BIT 0 ? Please document it
> + writel_relaxed(val, drvdata->base + TPDA_CR);
> + CS_LOCK(drvdata->base);
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(global_flush_req);
> +
> +static ssize_t cmbchan_mode_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode);
> +}
> +
> +static ssize_t cmbchan_mode_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + drvdata->cmbchan_mode = !!val;
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(cmbchan_mode);
Even this could go to the dev_ext_attribute magic and reuse a single
show/store.
> +
> +static struct attribute *tpda_attrs[] = {
> + &dev_attr_trig_async_enable.attr,
> + &dev_attr_trig_flag_ts_enable.attr,
> + &dev_attr_trig_freq_enable.attr,
> + &dev_attr_freq_ts_enable.attr,
> + &dev_attr_global_flush_req.attr,
> + &dev_attr_cmbchan_mode.attr,
> + NULL,
> +};
> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h
> index c6af3d2da3ef..0be625fb52fd 100644
> --- a/drivers/hwtracing/coresight/coresight-tpda.h
> +++ b/drivers/hwtracing/coresight/coresight-tpda.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #ifndef _CORESIGHT_CORESIGHT_TPDA_H
> @@ -8,6 +8,19 @@
>
> #define TPDA_CR (0x000)
> #define TPDA_Pn_CR(n) (0x004 + (n * 4))
> +#define TPDA_FPID_CR (0x084)
> +
> +/* Cross trigger FREQ packets timestamp bit */
> +#define TPDA_CR_FREQTS BIT(2)
> +/* Cross trigger FREQ packet request bit */
> +#define TPDA_CR_FRIE BIT(3)
> +/* Cross trigger FLAG packet request interface bit */
> +#define TPDA_CR_FLRIE BIT(4)
> +/* Cross trigger synchronization bit */
> +#define TPDA_CR_SRIE BIT(5)
> +/* Packetize CMB/MCMB traffic bit */
> +#define TPDA_CR_CMBCHANMODE BIT(20)
> +
Why are these not clubbed with the other TPDA_CR_ defintions ?
> /* Aggregator port enable bit */
> #define TPDA_Pn_CR_ENA BIT(0)
> /* Aggregator port CMB data set element size bit */
> @@ -19,6 +32,8 @@
>
> /* Bits 6 ~ 12 is for atid value */
> #define TPDA_CR_ATID GENMASK(12, 6)
> +/* Bits 13 ~ 19 is for mid value */
> +#define TPDA_CR_MID GENMASK(19, 13)
>
> /**
> * struct tpda_drvdata - specifics associated to an TPDA component
> @@ -29,6 +44,11 @@
> * @enable: enable status of the component.
> * @dsb_esize Record the DSB element size.
> * @cmb_esize Record the CMB element size.
> + * @trig_async: Enable/disable cross trigger synchronization sequence interface.
> + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request interface.
> + * @trig_freq: Enable/disable cross trigger FREQ packet request interface.
> + * @freq_ts: Enable/disable the timestamp for all FREQ packets.
> + * @cmbchan_mode: Configure the CMB/MCMB channel mode.
> */
> struct tpda_drvdata {
> void __iomem *base;
> @@ -38,6 +58,11 @@ struct tpda_drvdata {
> u8 atid;
> u32 dsb_esize;
> u32 cmb_esize;
> + bool trig_async;
> + bool trig_flag_ts;
> + bool trig_freq;
> + bool freq_ts;
> + bool cmbchan_mode;
> };
>
> #endif /* _CORESIGHT_CORESIGHT_TPDA_H */
Suzuki
On 12/18/2025 7:10 PM, Suzuki K Poulose wrote:
> On 28/10/2025 02:02, Jie Gan wrote:
>> From: Tao Zhang <tao.zhang@oss.qualcomm.com>
>>
>> Introduce sysfs nodes to configure cross-trigger parameters for TPDA.
>> These registers define the characteristics of cross-trigger packets,
>> including generation frequency and flag values.
>>
>> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com>
>> Reviewed-by: James Clark <james.clark@linaro.org>
>> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 ++++
>> drivers/hwtracing/coresight/coresight-tpda.c | 230 +++++++++++
>> ++++++++++
>> drivers/hwtracing/coresight/coresight-tpda.h | 27 ++-
>> 3 files changed, 299 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-
>> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
>> new file mode 100644
>> index 000000000000..80e4b05a1ab4
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
>> @@ -0,0 +1,43 @@
>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_async_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable cross trigger synchronization sequence
>> interface.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_flag_ts_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable cross trigger FLAG packet request interface.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_freq_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable cross trigger FREQ packet request interface.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/freq_ts_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable the timestamp for all FREQ packets.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/global_flush_req
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Set global (all ports) flush request bit. The bit
>> remains set until a
>> + global flush request sequence completes.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/cmbchan_mode
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Configure the CMB/MCMB channel mode for all enabled ports.
>> + Value 0 means raw channel mapping mode. Value 1 means channel
>> pair marking mode.
>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/
>> hwtracing/coresight/coresight-tpda.c
>> index 333b3cb23685..a9a27bcc65a1 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpda.c
>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
>> @@ -147,9 +147,37 @@ static void tpda_enable_pre_port(struct
>> tpda_drvdata *drvdata)
>> u32 val;
>> val = readl_relaxed(drvdata->base + TPDA_CR);
>> + val &= ~TPDA_CR_MID;
>> val &= ~TPDA_CR_ATID;
>
> See, below.
>
>> val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid);
>> + if (drvdata->trig_async)
>> + val |= TPDA_CR_SRIE;
>> + else
>> + val &= ~TPDA_CR_SRIE;
>> + if (drvdata->trig_flag_ts)
>> + val |= TPDA_CR_FLRIE;
>> + else
>> + val &= ~TPDA_CR_FLRIE;
>> + if (drvdata->trig_freq)
>> + val |= TPDA_CR_FRIE;
>> + else
>> + val &= ~TPDA_CR_FRIE;
>> + if (drvdata->freq_ts)
>> + val |= TPDA_CR_FREQTS;
>> + else
>> + val &= ~TPDA_CR_FREQTS;
>> + if (drvdata->cmbchan_mode)
>> + val |= TPDA_CR_CMBCHANMODE;
>> + else
>> + val &= ~TPDA_CR_CMBCHANMODE;
>
> Could we clear all of the bits that are configurable in one go in the
> beginning and set the appropriate ones based on the setting ? i.e.:
>
> Do we really need to retain any values ? And if not, why not start
> with a fresh set of values and avoid the read ?
Got it. We can start with a clean value and set the required bits,
without needing to read the register once.
>
>> writel_relaxed(val, drvdata->base + TPDA_CR);
>> +
>> + /*
>> + * If FLRIE bit is set, set the master and channel
>> + * id as zero
>> + */
>> + if (drvdata->trig_flag_ts)
>> + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR);
>> }
>> static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)
>> @@ -265,6 +293,206 @@ static const struct coresight_ops tpda_cs_ops = {
>> .link_ops = &tpda_link_ops,
>> };
>> +static ssize_t trig_async_enable_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> +
>> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async);
>> +}
>> +
>> +static ssize_t trig_async_enable_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + drvdata->trig_async = !!val;
>> +
>
>
>
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(trig_async_enable);
>
> ...
>
>> +static DEVICE_ATTR_RW(trig_flag_ts_enable);
>
> ...
>
>> +static DEVICE_ATTR_RW(trig_freq_enable);
>
> ...
>> +static DEVICE_ATTR_RW(freq_ts_enable);
>
> These attribute are boolean and looks like we could save some space on
> code by using dev_ext_attribute.
> see tpdm_simple_dataset_rw()/tpdm_simple_dataset_ro() . You could
>
> #define TPDA_TRIG_ASYNC 0
> #define TPDA_TRIG_FLAG_TS 1
> #define TPDA_TRIG_FREQ 2
>
>
> tpda_trig_sysfs_show/store()
>
> bool *ptr;
> switch (eattr->var) {
> case TPDA_TRIG_ASYNC:
> ptr = &drvdata->trig_async;
> break;
> case TPDA_TRIG_FLAG_TS:
> ptr = &drvdata->trig_flag_ts;
> break;
> ...
>
> }
>
Will wrap in tpda_trig_sysfs_show/store().
>
>
>> +
>> +static ssize_t global_flush_req_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (!drvdata->csdev->refcnt)
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + CS_UNLOCK(drvdata->base);
>> + val = readl_relaxed(drvdata->base + TPDA_CR);
>> + CS_LOCK(drvdata->base);
>> + /* Only read value for bit 0 */
>> + val &= BIT(0);
>> +
>> + return sysfs_emit(buf, "%lu\n", val);
>> +}
>> +
>> +static ssize_t global_flush_req_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + if (!drvdata->csdev->refcnt || !val)
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + CS_UNLOCK(drvdata->base);
>> + val = readl_relaxed(drvdata->base + TPDA_CR);
>> + /* Only set bit 0 */
>> + val |= BIT(0);
>
> What is BIT 0 ? Please document it
will document it.
Bit0 is Global (all ports) flush request bit.
Set 1 means a flush request is made for all ports.
>
>> + writel_relaxed(val, drvdata->base + TPDA_CR);
>> + CS_LOCK(drvdata->base);
>> +
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(global_flush_req);
>
>
>
>> +
>> +static ssize_t cmbchan_mode_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> +
>> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode);
>> +}
>> +
>> +static ssize_t cmbchan_mode_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + drvdata->cmbchan_mode = !!val;
>> +
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(cmbchan_mode);
>
> Even this could go to the dev_ext_attribute magic and reuse a single
> show/store.
Got it.
>
>> +
>> +static struct attribute *tpda_attrs[] = {
>> + &dev_attr_trig_async_enable.attr,
>> + &dev_attr_trig_flag_ts_enable.attr,
>> + &dev_attr_trig_freq_enable.attr,
>> + &dev_attr_freq_ts_enable.attr,
>> + &dev_attr_global_flush_req.attr,
>> + &dev_attr_cmbchan_mode.attr,
>> + NULL,
>> +};
>
>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/
>> hwtracing/coresight/coresight-tpda.h
>> index c6af3d2da3ef..0be625fb52fd 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpda.h
>> +++ b/drivers/hwtracing/coresight/coresight-tpda.h
>> @@ -1,6 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0 */
>> /*
>> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> */
>> #ifndef _CORESIGHT_CORESIGHT_TPDA_H
>> @@ -8,6 +8,19 @@
>> #define TPDA_CR (0x000)
>> #define TPDA_Pn_CR(n) (0x004 + (n * 4))
>> +#define TPDA_FPID_CR (0x084)
>> +
>> +/* Cross trigger FREQ packets timestamp bit */
>> +#define TPDA_CR_FREQTS BIT(2)
>> +/* Cross trigger FREQ packet request bit */
>> +#define TPDA_CR_FRIE BIT(3)
>> +/* Cross trigger FLAG packet request interface bit */
>> +#define TPDA_CR_FLRIE BIT(4)
>> +/* Cross trigger synchronization bit */
>> +#define TPDA_CR_SRIE BIT(5)
>> +/* Packetize CMB/MCMB traffic bit */
>> +#define TPDA_CR_CMBCHANMODE BIT(20)
>> +
>
> Why are these not clubbed with the other TPDA_CR_ defintions ?
I should put this bit after:
/* Bits 6 ~ 12 is for atid value */
#define TPDA_CR_ATID GENMASK(12, 6)
+/* Bits 13 ~ 19 is for mid value */
+#define TPDA_CR_MID GENMASK(19, 13)
MID here is the master ID which is used to identify the TPDA device
itself in received packets when multiple tpda devices are enabled.
Thanks,
Jie
>
>> /* Aggregator port enable bit */
>> #define TPDA_Pn_CR_ENA BIT(0)
>> /* Aggregator port CMB data set element size bit */
>> @@ -19,6 +32,8 @@
>> /* Bits 6 ~ 12 is for atid value */
>> #define TPDA_CR_ATID GENMASK(12, 6)
>> +/* Bits 13 ~ 19 is for mid value */
>> +#define TPDA_CR_MID GENMASK(19, 13)
>> /**
>> * struct tpda_drvdata - specifics associated to an TPDA component
>> @@ -29,6 +44,11 @@
>> * @enable: enable status of the component.
>> * @dsb_esize Record the DSB element size.
>> * @cmb_esize Record the CMB element size.
>> + * @trig_async: Enable/disable cross trigger synchronization
>> sequence interface.
>> + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request
>> interface.
>> + * @trig_freq: Enable/disable cross trigger FREQ packet request
>> interface.
>> + * @freq_ts: Enable/disable the timestamp for all FREQ packets.
>> + * @cmbchan_mode: Configure the CMB/MCMB channel mode.
>> */
>> struct tpda_drvdata {
>> void __iomem *base;
>> @@ -38,6 +58,11 @@ struct tpda_drvdata {
>> u8 atid;
>> u32 dsb_esize;
>> u32 cmb_esize;
>> + bool trig_async;
>> + bool trig_flag_ts;
>> + bool trig_freq;
>> + bool freq_ts;
>> + bool cmbchan_mode;
>> };
>> #endif /* _CORESIGHT_CORESIGHT_TPDA_H */
>
> Suzuki
>
On 18/12/2025 11:10, Suzuki K Poulose wrote:
> On 28/10/2025 02:02, Jie Gan wrote:
>> From: Tao Zhang <tao.zhang@oss.qualcomm.com>
>>
>> Introduce sysfs nodes to configure cross-trigger parameters for TPDA.
>> These registers define the characteristics of cross-trigger packets,
>> including generation frequency and flag values.
>>
>> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com>
>> Reviewed-by: James Clark <james.clark@linaro.org>
>> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 ++++
>> drivers/hwtracing/coresight/coresight-tpda.c | 230 +++++++++++
>> ++++++++++
>> drivers/hwtracing/coresight/coresight-tpda.h | 27 ++-
>> 3 files changed, 299 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-
>> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
>> new file mode 100644
>> index 000000000000..80e4b05a1ab4
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
>> @@ -0,0 +1,43 @@
>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_async_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable cross trigger synchronization sequence
>> interface.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_flag_ts_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable cross trigger FLAG packet request interface.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_freq_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable cross trigger FREQ packet request interface.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/freq_ts_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable the timestamp for all FREQ packets.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/global_flush_req
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Set global (all ports) flush request bit. The bit
>> remains set until a
>> + global flush request sequence completes.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/cmbchan_mode
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Configure the CMB/MCMB channel mode for all enabled ports.
>> + Value 0 means raw channel mapping mode. Value 1 means channel
>> pair marking mode.
>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/
>> hwtracing/coresight/coresight-tpda.c
>> index 333b3cb23685..a9a27bcc65a1 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpda.c
>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
>> @@ -147,9 +147,37 @@ static void tpda_enable_pre_port(struct
>> tpda_drvdata *drvdata)
>> u32 val;
>> val = readl_relaxed(drvdata->base + TPDA_CR);
>> + val &= ~TPDA_CR_MID;
>> val &= ~TPDA_CR_ATID;
>
> See, below.
>
>> val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid);
>> + if (drvdata->trig_async)
>> + val |= TPDA_CR_SRIE;
>> + else
>> + val &= ~TPDA_CR_SRIE;
>> + if (drvdata->trig_flag_ts)
>> + val |= TPDA_CR_FLRIE;
>> + else
>> + val &= ~TPDA_CR_FLRIE;
>> + if (drvdata->trig_freq)
>> + val |= TPDA_CR_FRIE;
>> + else
>> + val &= ~TPDA_CR_FRIE;
>> + if (drvdata->freq_ts)
>> + val |= TPDA_CR_FREQTS;
>> + else
>> + val &= ~TPDA_CR_FREQTS;
>> + if (drvdata->cmbchan_mode)
>> + val |= TPDA_CR_CMBCHANMODE;
>> + else
>> + val &= ~TPDA_CR_CMBCHANMODE;
>
> Could we clear all of the bits that are configurable in one go in the
> beginning and set the appropriate ones based on the setting ? i.e.:
>
> Do we really need to retain any values ? And if not, why not start
> with a fresh set of values and avoid the read ?
>
>> writel_relaxed(val, drvdata->base + TPDA_CR);
>> +
>> + /*
>> + * If FLRIE bit is set, set the master and channel
>> + * id as zero
>> + */
>> + if (drvdata->trig_flag_ts)
>> + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR);
>> }
>> static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)
>> @@ -265,6 +293,206 @@ static const struct coresight_ops tpda_cs_ops = {
>> .link_ops = &tpda_link_ops,
>> };
>> +static ssize_t trig_async_enable_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> +
>> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async);
>> +}
>> +
>> +static ssize_t trig_async_enable_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + drvdata->trig_async = !!val;
>> +
>
>
>
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(trig_async_enable);
>
> ...
>
>> +static DEVICE_ATTR_RW(trig_flag_ts_enable);
>
> ...
>
>> +static DEVICE_ATTR_RW(trig_freq_enable);
>
> ...
>> +static DEVICE_ATTR_RW(freq_ts_enable);
>
> These attribute are boolean and looks like we could save some space on
> code by using dev_ext_attribute.
> see tpdm_simple_dataset_rw()/tpdm_simple_dataset_ro() . You could
>
> #define TPDA_TRIG_ASYNC 0
> #define TPDA_TRIG_FLAG_TS 1
> #define TPDA_TRIG_FREQ 2
>
>
> tpda_trig_sysfs_show/store()
>
> bool *ptr;
> switch (eattr->var) {
> case TPDA_TRIG_ASYNC:
> ptr = &drvdata->trig_async;
> break;
> case TPDA_TRIG_FLAG_TS:
> ptr = &drvdata->trig_flag_ts;
> break;
> ...
>
> }
>
>
>
-->8--
Cut here
>> +
>> +static ssize_t global_flush_req_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (!drvdata->csdev->refcnt)
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + CS_UNLOCK(drvdata->base);
>> + val = readl_relaxed(drvdata->base + TPDA_CR);
>> + CS_LOCK(drvdata->base);
>> + /* Only read value for bit 0 */
>> + val &= BIT(0);
>> +
>> + return sysfs_emit(buf, "%lu\n", val);
>> +}
>> +
>> +static ssize_t global_flush_req_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + if (!drvdata->csdev->refcnt || !val)
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + CS_UNLOCK(drvdata->base);
>> + val = readl_relaxed(drvdata->base + TPDA_CR);
>> + /* Only set bit 0 */
>> + val |= BIT(0);
>
> What is BIT 0 ? Please document it
>
>> + writel_relaxed(val, drvdata->base + TPDA_CR);
>> + CS_LOCK(drvdata->base);
>> +
>> + return size;
>> +}
Also this, global_flush_req seems to be a separate change from the rest
of the additions in the patch. Why not split it into a separate patch
with appropriate description of what this is for ?
Suzuki
On 12/18/2025 7:20 PM, Suzuki K Poulose wrote:
> On 18/12/2025 11:10, Suzuki K Poulose wrote:
>> On 28/10/2025 02:02, Jie Gan wrote:
>>> From: Tao Zhang <tao.zhang@oss.qualcomm.com>
>>>
>>> Introduce sysfs nodes to configure cross-trigger parameters for TPDA.
>>> These registers define the characteristics of cross-trigger packets,
>>> including generation frequency and flag values.
>>>
>>> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com>
>>> Reviewed-by: James Clark <james.clark@linaro.org>
>>> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com>
>>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>>> ---
>>> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 ++++
>>> drivers/hwtracing/coresight/coresight-tpda.c | 230 ++++++++++
>>> + ++++++++++
>>> drivers/hwtracing/coresight/coresight-tpda.h | 27 ++-
>>> 3 files changed, 299 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-
>>> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
>>> new file mode 100644
>>> index 000000000000..80e4b05a1ab4
>>> --- /dev/null
>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
>>> @@ -0,0 +1,43 @@
>>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_async_enable
>>> +Date: October 2025
>>> +KernelVersion: 6.19
>>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>>> +Description:
>>> + (RW) Enable/disable cross trigger synchronization sequence
>>> interface.
>>> +
>>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_flag_ts_enable
>>> +Date: October 2025
>>> +KernelVersion: 6.19
>>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>>> +Description:
>>> + (RW) Enable/disable cross trigger FLAG packet request
>>> interface.
>>> +
>>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_freq_enable
>>> +Date: October 2025
>>> +KernelVersion: 6.19
>>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>>> +Description:
>>> + (RW) Enable/disable cross trigger FREQ packet request
>>> interface.
>>> +
>>> +What: /sys/bus/coresight/devices/<tpda-name>/freq_ts_enable
>>> +Date: October 2025
>>> +KernelVersion: 6.19
>>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>>> +Description:
>>> + (RW) Enable/disable the timestamp for all FREQ packets.
>>> +
>>> +What: /sys/bus/coresight/devices/<tpda-name>/global_flush_req
>>> +Date: October 2025
>>> +KernelVersion: 6.19
>>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>>> +Description:
>>> + (RW) Set global (all ports) flush request bit. The bit
>>> remains set until a
>>> + global flush request sequence completes.
>>> +
>>> +What: /sys/bus/coresight/devices/<tpda-name>/cmbchan_mode
>>> +Date: October 2025
>>> +KernelVersion: 6.19
>>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>>> +Description:
>>> + (RW) Configure the CMB/MCMB channel mode for all enabled ports.
>>> + Value 0 means raw channel mapping mode. Value 1 means
>>> channel pair marking mode.
>>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/
>>> hwtracing/coresight/coresight-tpda.c
>>> index 333b3cb23685..a9a27bcc65a1 100644
>>> --- a/drivers/hwtracing/coresight/coresight-tpda.c
>>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
>>> @@ -147,9 +147,37 @@ static void tpda_enable_pre_port(struct
>>> tpda_drvdata *drvdata)
>>> u32 val;
>>> val = readl_relaxed(drvdata->base + TPDA_CR);
>>> + val &= ~TPDA_CR_MID;
>>> val &= ~TPDA_CR_ATID;
>>
>> See, below.
>>
>>> val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid);
>>> + if (drvdata->trig_async)
>>> + val |= TPDA_CR_SRIE;
>>> + else
>>> + val &= ~TPDA_CR_SRIE;
>>> + if (drvdata->trig_flag_ts)
>>> + val |= TPDA_CR_FLRIE;
>>> + else
>>> + val &= ~TPDA_CR_FLRIE;
>>> + if (drvdata->trig_freq)
>>> + val |= TPDA_CR_FRIE;
>>> + else
>>> + val &= ~TPDA_CR_FRIE;
>>> + if (drvdata->freq_ts)
>>> + val |= TPDA_CR_FREQTS;
>>> + else
>>> + val &= ~TPDA_CR_FREQTS;
>>> + if (drvdata->cmbchan_mode)
>>> + val |= TPDA_CR_CMBCHANMODE;
>>> + else
>>> + val &= ~TPDA_CR_CMBCHANMODE;
>>
>> Could we clear all of the bits that are configurable in one go in the
>> beginning and set the appropriate ones based on the setting ? i.e.:
>>
>> Do we really need to retain any values ? And if not, why not start
>> with a fresh set of values and avoid the read ?
>>
>>> writel_relaxed(val, drvdata->base + TPDA_CR);
>>> +
>>> + /*
>>> + * If FLRIE bit is set, set the master and channel
>>> + * id as zero
>>> + */
>>> + if (drvdata->trig_flag_ts)
>>> + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR);
>>> }
>>> static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)
>>> @@ -265,6 +293,206 @@ static const struct coresight_ops tpda_cs_ops = {
>>> .link_ops = &tpda_link_ops,
>>> };
>>> +static ssize_t trig_async_enable_show(struct device *dev,
>>> + struct device_attribute *attr,
>>> + char *buf)
>>> +{
>>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>>> +
>>> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async);
>>> +}
>>> +
>>> +static ssize_t trig_async_enable_store(struct device *dev,
>>> + struct device_attribute *attr,
>>> + const char *buf,
>>> + size_t size)
>>> +{
>>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>>> + unsigned long val;
>>> +
>>> + if (kstrtoul(buf, 0, &val))
>>> + return -EINVAL;
>>> +
>>> + guard(spinlock)(&drvdata->spinlock);
>>> + drvdata->trig_async = !!val;
>>> +
>>
>>
>>
>>> + return size;
>>> +}
>>> +static DEVICE_ATTR_RW(trig_async_enable);
>>
>> ...
>>
>>> +static DEVICE_ATTR_RW(trig_flag_ts_enable);
>>
>> ...
>>
>>> +static DEVICE_ATTR_RW(trig_freq_enable);
>>
>> ...
>>> +static DEVICE_ATTR_RW(freq_ts_enable);
>>
>> These attribute are boolean and looks like we could save some space on
>> code by using dev_ext_attribute.
>> see tpdm_simple_dataset_rw()/tpdm_simple_dataset_ro() . You could
>>
>> #define TPDA_TRIG_ASYNC 0
>> #define TPDA_TRIG_FLAG_TS 1
>> #define TPDA_TRIG_FREQ 2
>>
>>
>> tpda_trig_sysfs_show/store()
>>
>> bool *ptr;
>> switch (eattr->var) {
>> case TPDA_TRIG_ASYNC:
>> ptr = &drvdata->trig_async;
>> break;
>> case TPDA_TRIG_FLAG_TS:
>> ptr = &drvdata->trig_flag_ts;
>> break;
>> ...
>>
>> }
>>
>>
>>
>
> -->8--
>
> Cut here
>
>>> +
>>> +static ssize_t global_flush_req_show(struct device *dev,
>>> + struct device_attribute *attr,
>>> + char *buf)
>>> +{
>>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>>> + unsigned long val;
>>> +
>>> + if (!drvdata->csdev->refcnt)
>>> + return -EINVAL;
>>> +
>>> + guard(spinlock)(&drvdata->spinlock);
>>> + CS_UNLOCK(drvdata->base);
>>> + val = readl_relaxed(drvdata->base + TPDA_CR);
>>> + CS_LOCK(drvdata->base);
>>> + /* Only read value for bit 0 */
>>> + val &= BIT(0);
>>> +
>>> + return sysfs_emit(buf, "%lu\n", val);
>>> +}
>>> +
>>> +static ssize_t global_flush_req_store(struct device *dev,
>>> + struct device_attribute *attr,
>>> + const char *buf,
>>> + size_t size)
>>> +{
>>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>>> + unsigned long val;
>>> +
>>> + if (kstrtoul(buf, 0, &val))
>>> + return -EINVAL;
>>> +
>>> + if (!drvdata->csdev->refcnt || !val)
>>> + return -EINVAL;
>>> +
>>> + guard(spinlock)(&drvdata->spinlock);
>>> + CS_UNLOCK(drvdata->base);
>>> + val = readl_relaxed(drvdata->base + TPDA_CR);
>>> + /* Only set bit 0 */
>>> + val |= BIT(0);
>>
>> What is BIT 0 ? Please document it
>>
>>> + writel_relaxed(val, drvdata->base + TPDA_CR);
>>> + CS_LOCK(drvdata->base);
>>> +
>>> + return size;
>>> +}
>
> Also this, global_flush_req seems to be a separate change from the rest
> of the additions in the patch. Why not split it into a separate patch
> with appropriate description of what this is for ?
Hi Suzuki,
global_flush_req is part of the TPDA_CR register, it's the bit0 of the
register.
I should document it in header file:
/* Cross trigger Global (all ports) flush request bit */
#define TPDA_CR_FLREQ BIT(0)
We also have below bit that is not in use:
#define TPDA_CR_FREQREQ BIT(1)
It's frequency request bit, that determines the frequency for generating
frequency packets.
Thanks,
Jie
>
> Suzuki
On 10/28/2025 10:02 AM, Jie Gan wrote:
> From: Tao Zhang <tao.zhang@oss.qualcomm.com>
>
> Introduce sysfs nodes to configure cross-trigger parameters for TPDA.
> These registers define the characteristics of cross-trigger packets,
> including generation frequency and flag values.
>
> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com>
> Reviewed-by: James Clark <james.clark@linaro.org>
> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 ++++
> drivers/hwtracing/coresight/coresight-tpda.c | 230 +++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpda.h | 27 ++-
> 3 files changed, 299 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
> new file mode 100644
> index 000000000000..80e4b05a1ab4
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
Gentle reminder.
Do I need update the date and the kernelVersion of the sysfs
node?(target 7.0?)
Thanks,
Jie
> @@ -0,0 +1,43 @@
> +What: /sys/bus/coresight/devices/<tpda-name>/trig_async_enable
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Enable/disable cross trigger synchronization sequence interface.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/trig_flag_ts_enable
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Enable/disable cross trigger FLAG packet request interface.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/trig_freq_enable
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Enable/disable cross trigger FREQ packet request interface.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/freq_ts_enable
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Enable/disable the timestamp for all FREQ packets.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/global_flush_req
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Set global (all ports) flush request bit. The bit remains set until a
> + global flush request sequence completes.
> +
> +What: /sys/bus/coresight/devices/<tpda-name>/cmbchan_mode
> +Date: October 2025
> +KernelVersion: 6.19
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
> +Description:
> + (RW) Configure the CMB/MCMB channel mode for all enabled ports.
> + Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode.
> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c
> index 333b3cb23685..a9a27bcc65a1 100644
> --- a/drivers/hwtracing/coresight/coresight-tpda.c
> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
> @@ -147,9 +147,37 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)
> u32 val;
>
> val = readl_relaxed(drvdata->base + TPDA_CR);
> + val &= ~TPDA_CR_MID;
> val &= ~TPDA_CR_ATID;
> val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid);
> + if (drvdata->trig_async)
> + val |= TPDA_CR_SRIE;
> + else
> + val &= ~TPDA_CR_SRIE;
> + if (drvdata->trig_flag_ts)
> + val |= TPDA_CR_FLRIE;
> + else
> + val &= ~TPDA_CR_FLRIE;
> + if (drvdata->trig_freq)
> + val |= TPDA_CR_FRIE;
> + else
> + val &= ~TPDA_CR_FRIE;
> + if (drvdata->freq_ts)
> + val |= TPDA_CR_FREQTS;
> + else
> + val &= ~TPDA_CR_FREQTS;
> + if (drvdata->cmbchan_mode)
> + val |= TPDA_CR_CMBCHANMODE;
> + else
> + val &= ~TPDA_CR_CMBCHANMODE;
> writel_relaxed(val, drvdata->base + TPDA_CR);
> +
> + /*
> + * If FLRIE bit is set, set the master and channel
> + * id as zero
> + */
> + if (drvdata->trig_flag_ts)
> + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR);
> }
>
> static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)
> @@ -265,6 +293,206 @@ static const struct coresight_ops tpda_cs_ops = {
> .link_ops = &tpda_link_ops,
> };
>
> +static ssize_t trig_async_enable_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async);
> +}
> +
> +static ssize_t trig_async_enable_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + drvdata->trig_async = !!val;
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(trig_async_enable);
> +
> +static ssize_t trig_flag_ts_enable_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts);
> +}
> +
> +static ssize_t trig_flag_ts_enable_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + drvdata->trig_flag_ts = !!val;
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(trig_flag_ts_enable);
> +
> +static ssize_t trig_freq_enable_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq);
> +}
> +
> +static ssize_t trig_freq_enable_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + drvdata->trig_freq = !!val;
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(trig_freq_enable);
> +
> +static ssize_t freq_ts_enable_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts);
> +}
> +
> +static ssize_t freq_ts_enable_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + drvdata->freq_ts = !!val;
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(freq_ts_enable);
> +
> +static ssize_t global_flush_req_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (!drvdata->csdev->refcnt)
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + CS_UNLOCK(drvdata->base);
> + val = readl_relaxed(drvdata->base + TPDA_CR);
> + CS_LOCK(drvdata->base);
> + /* Only read value for bit 0 */
> + val &= BIT(0);
> +
> + return sysfs_emit(buf, "%lu\n", val);
> +}
> +
> +static ssize_t global_flush_req_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + if (!drvdata->csdev->refcnt || !val)
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + CS_UNLOCK(drvdata->base);
> + val = readl_relaxed(drvdata->base + TPDA_CR);
> + /* Only set bit 0 */
> + val |= BIT(0);
> + writel_relaxed(val, drvdata->base + TPDA_CR);
> + CS_LOCK(drvdata->base);
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(global_flush_req);
> +
> +static ssize_t cmbchan_mode_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode);
> +}
> +
> +static ssize_t cmbchan_mode_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + guard(spinlock)(&drvdata->spinlock);
> + drvdata->cmbchan_mode = !!val;
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(cmbchan_mode);
> +
> +static struct attribute *tpda_attrs[] = {
> + &dev_attr_trig_async_enable.attr,
> + &dev_attr_trig_flag_ts_enable.attr,
> + &dev_attr_trig_freq_enable.attr,
> + &dev_attr_freq_ts_enable.attr,
> + &dev_attr_global_flush_req.attr,
> + &dev_attr_cmbchan_mode.attr,
> + NULL,
> +};
> +
> +static struct attribute_group tpda_attr_grp = {
> + .attrs = tpda_attrs,
> +};
> +
> +static const struct attribute_group *tpda_attr_grps[] = {
> + &tpda_attr_grp,
> + NULL,
> +};
> +
> static int tpda_init_default_data(struct tpda_drvdata *drvdata)
> {
> int atid;
> @@ -280,6 +508,7 @@ static int tpda_init_default_data(struct tpda_drvdata *drvdata)
> return atid;
>
> drvdata->atid = atid;
> + drvdata->freq_ts = true;
> return 0;
> }
>
> @@ -323,6 +552,7 @@ static int tpda_probe(struct amba_device *adev, const struct amba_id *id)
> desc.ops = &tpda_cs_ops;
> desc.pdata = adev->dev.platform_data;
> desc.dev = &adev->dev;
> + desc.groups = tpda_attr_grps;
> desc.access = CSDEV_ACCESS_IOMEM(base);
> drvdata->csdev = coresight_register(&desc);
> if (IS_ERR(drvdata->csdev))
> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h
> index c6af3d2da3ef..0be625fb52fd 100644
> --- a/drivers/hwtracing/coresight/coresight-tpda.h
> +++ b/drivers/hwtracing/coresight/coresight-tpda.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #ifndef _CORESIGHT_CORESIGHT_TPDA_H
> @@ -8,6 +8,19 @@
>
> #define TPDA_CR (0x000)
> #define TPDA_Pn_CR(n) (0x004 + (n * 4))
> +#define TPDA_FPID_CR (0x084)
> +
> +/* Cross trigger FREQ packets timestamp bit */
> +#define TPDA_CR_FREQTS BIT(2)
> +/* Cross trigger FREQ packet request bit */
> +#define TPDA_CR_FRIE BIT(3)
> +/* Cross trigger FLAG packet request interface bit */
> +#define TPDA_CR_FLRIE BIT(4)
> +/* Cross trigger synchronization bit */
> +#define TPDA_CR_SRIE BIT(5)
> +/* Packetize CMB/MCMB traffic bit */
> +#define TPDA_CR_CMBCHANMODE BIT(20)
> +
> /* Aggregator port enable bit */
> #define TPDA_Pn_CR_ENA BIT(0)
> /* Aggregator port CMB data set element size bit */
> @@ -19,6 +32,8 @@
>
> /* Bits 6 ~ 12 is for atid value */
> #define TPDA_CR_ATID GENMASK(12, 6)
> +/* Bits 13 ~ 19 is for mid value */
> +#define TPDA_CR_MID GENMASK(19, 13)
>
> /**
> * struct tpda_drvdata - specifics associated to an TPDA component
> @@ -29,6 +44,11 @@
> * @enable: enable status of the component.
> * @dsb_esize Record the DSB element size.
> * @cmb_esize Record the CMB element size.
> + * @trig_async: Enable/disable cross trigger synchronization sequence interface.
> + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request interface.
> + * @trig_freq: Enable/disable cross trigger FREQ packet request interface.
> + * @freq_ts: Enable/disable the timestamp for all FREQ packets.
> + * @cmbchan_mode: Configure the CMB/MCMB channel mode.
> */
> struct tpda_drvdata {
> void __iomem *base;
> @@ -38,6 +58,11 @@ struct tpda_drvdata {
> u8 atid;
> u32 dsb_esize;
> u32 cmb_esize;
> + bool trig_async;
> + bool trig_flag_ts;
> + bool trig_freq;
> + bool freq_ts;
> + bool cmbchan_mode;
> };
>
> #endif /* _CORESIGHT_CORESIGHT_TPDA_H */
>
On 18/12/2025 06:22, Jie Gan wrote:
>
>
> On 10/28/2025 10:02 AM, Jie Gan wrote:
>> From: Tao Zhang <tao.zhang@oss.qualcomm.com>
>>
>> Introduce sysfs nodes to configure cross-trigger parameters for TPDA.
>> These registers define the characteristics of cross-trigger packets,
>> including generation frequency and flag values.
>>
>> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com>
>> Reviewed-by: James Clark <james.clark@linaro.org>
>> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 ++++
>> drivers/hwtracing/coresight/coresight-tpda.c | 230 +++++++++++
>> ++++++++++
>> drivers/hwtracing/coresight/coresight-tpda.h | 27 ++-
>> 3 files changed, 299 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-
>> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
>> new file mode 100644
>> index 000000000000..80e4b05a1ab4
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
>
> Gentle reminder.
>
> Do I need update the date and the kernelVersion of the sysfs node?
> (target 7.0?)
Leave it with me, I can fix it up. Apologies for missing this out.
Suzuki
>
> Thanks,
> Jie
>
>
>> @@ -0,0 +1,43 @@
>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_async_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable cross trigger synchronization sequence
>> interface.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_flag_ts_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable cross trigger FLAG packet request interface.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/trig_freq_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable cross trigger FREQ packet request interface.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/freq_ts_enable
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Enable/disable the timestamp for all FREQ packets.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/global_flush_req
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Set global (all ports) flush request bit. The bit
>> remains set until a
>> + global flush request sequence completes.
>> +
>> +What: /sys/bus/coresight/devices/<tpda-name>/cmbchan_mode
>> +Date: October 2025
>> +KernelVersion: 6.19
>> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang
>> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
>> +Description:
>> + (RW) Configure the CMB/MCMB channel mode for all enabled ports.
>> + Value 0 means raw channel mapping mode. Value 1 means channel
>> pair marking mode.
>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/
>> hwtracing/coresight/coresight-tpda.c
>> index 333b3cb23685..a9a27bcc65a1 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpda.c
>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
>> @@ -147,9 +147,37 @@ static void tpda_enable_pre_port(struct
>> tpda_drvdata *drvdata)
>> u32 val;
>> val = readl_relaxed(drvdata->base + TPDA_CR);
>> + val &= ~TPDA_CR_MID;
>> val &= ~TPDA_CR_ATID;
>> val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid);
>> + if (drvdata->trig_async)
>> + val |= TPDA_CR_SRIE;
>> + else
>> + val &= ~TPDA_CR_SRIE;
>> + if (drvdata->trig_flag_ts)
>> + val |= TPDA_CR_FLRIE;
>> + else
>> + val &= ~TPDA_CR_FLRIE;
>> + if (drvdata->trig_freq)
>> + val |= TPDA_CR_FRIE;
>> + else
>> + val &= ~TPDA_CR_FRIE;
>> + if (drvdata->freq_ts)
>> + val |= TPDA_CR_FREQTS;
>> + else
>> + val &= ~TPDA_CR_FREQTS;
>> + if (drvdata->cmbchan_mode)
>> + val |= TPDA_CR_CMBCHANMODE;
>> + else
>> + val &= ~TPDA_CR_CMBCHANMODE;
>> writel_relaxed(val, drvdata->base + TPDA_CR);
>> +
>> + /*
>> + * If FLRIE bit is set, set the master and channel
>> + * id as zero
>> + */
>> + if (drvdata->trig_flag_ts)
>> + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR);
>> }
>> static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)
>> @@ -265,6 +293,206 @@ static const struct coresight_ops tpda_cs_ops = {
>> .link_ops = &tpda_link_ops,
>> };
>> +static ssize_t trig_async_enable_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> +
>> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async);
>> +}
>> +
>> +static ssize_t trig_async_enable_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + drvdata->trig_async = !!val;
>> +
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(trig_async_enable);
>> +
>> +static ssize_t trig_flag_ts_enable_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> +
>> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts);
>> +}
>> +
>> +static ssize_t trig_flag_ts_enable_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + drvdata->trig_flag_ts = !!val;
>> +
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(trig_flag_ts_enable);
>> +
>> +static ssize_t trig_freq_enable_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> +
>> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq);
>> +}
>> +
>> +static ssize_t trig_freq_enable_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + drvdata->trig_freq = !!val;
>> +
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(trig_freq_enable);
>> +
>> +static ssize_t freq_ts_enable_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> +
>> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts);
>> +}
>> +
>> +static ssize_t freq_ts_enable_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + drvdata->freq_ts = !!val;
>> +
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(freq_ts_enable);
>> +
>> +static ssize_t global_flush_req_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (!drvdata->csdev->refcnt)
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + CS_UNLOCK(drvdata->base);
>> + val = readl_relaxed(drvdata->base + TPDA_CR);
>> + CS_LOCK(drvdata->base);
>> + /* Only read value for bit 0 */
>> + val &= BIT(0);
>> +
>> + return sysfs_emit(buf, "%lu\n", val);
>> +}
>> +
>> +static ssize_t global_flush_req_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + if (!drvdata->csdev->refcnt || !val)
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + CS_UNLOCK(drvdata->base);
>> + val = readl_relaxed(drvdata->base + TPDA_CR);
>> + /* Only set bit 0 */
>> + val |= BIT(0);
>> + writel_relaxed(val, drvdata->base + TPDA_CR);
>> + CS_LOCK(drvdata->base);
>> +
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(global_flush_req);
>> +
>> +static ssize_t cmbchan_mode_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> +
>> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode);
>> +}
>> +
>> +static ssize_t cmbchan_mode_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + unsigned long val;
>> +
>> + if (kstrtoul(buf, 0, &val))
>> + return -EINVAL;
>> +
>> + guard(spinlock)(&drvdata->spinlock);
>> + drvdata->cmbchan_mode = !!val;
>> +
>> + return size;
>> +}
>> +static DEVICE_ATTR_RW(cmbchan_mode);
>> +
>> +static struct attribute *tpda_attrs[] = {
>> + &dev_attr_trig_async_enable.attr,
>> + &dev_attr_trig_flag_ts_enable.attr,
>> + &dev_attr_trig_freq_enable.attr,
>> + &dev_attr_freq_ts_enable.attr,
>> + &dev_attr_global_flush_req.attr,
>> + &dev_attr_cmbchan_mode.attr,
>> + NULL,
>> +};
>> +
>> +static struct attribute_group tpda_attr_grp = {
>> + .attrs = tpda_attrs,
>> +};
>> +
>> +static const struct attribute_group *tpda_attr_grps[] = {
>> + &tpda_attr_grp,
>> + NULL,
>> +};
>> +
>> static int tpda_init_default_data(struct tpda_drvdata *drvdata)
>> {
>> int atid;
>> @@ -280,6 +508,7 @@ static int tpda_init_default_data(struct
>> tpda_drvdata *drvdata)
>> return atid;
>> drvdata->atid = atid;
>> + drvdata->freq_ts = true;
>> return 0;
>> }
>> @@ -323,6 +552,7 @@ static int tpda_probe(struct amba_device *adev,
>> const struct amba_id *id)
>> desc.ops = &tpda_cs_ops;
>> desc.pdata = adev->dev.platform_data;
>> desc.dev = &adev->dev;
>> + desc.groups = tpda_attr_grps;
>> desc.access = CSDEV_ACCESS_IOMEM(base);
>> drvdata->csdev = coresight_register(&desc);
>> if (IS_ERR(drvdata->csdev))
>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/
>> hwtracing/coresight/coresight-tpda.h
>> index c6af3d2da3ef..0be625fb52fd 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpda.h
>> +++ b/drivers/hwtracing/coresight/coresight-tpda.h
>> @@ -1,6 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0 */
>> /*
>> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> */
>> #ifndef _CORESIGHT_CORESIGHT_TPDA_H
>> @@ -8,6 +8,19 @@
>> #define TPDA_CR (0x000)
>> #define TPDA_Pn_CR(n) (0x004 + (n * 4))
>> +#define TPDA_FPID_CR (0x084)
>> +
>> +/* Cross trigger FREQ packets timestamp bit */
>> +#define TPDA_CR_FREQTS BIT(2)
>> +/* Cross trigger FREQ packet request bit */
>> +#define TPDA_CR_FRIE BIT(3)
>> +/* Cross trigger FLAG packet request interface bit */
>> +#define TPDA_CR_FLRIE BIT(4)
>> +/* Cross trigger synchronization bit */
>> +#define TPDA_CR_SRIE BIT(5)
>> +/* Packetize CMB/MCMB traffic bit */
>> +#define TPDA_CR_CMBCHANMODE BIT(20)
>> +
>> /* Aggregator port enable bit */
>> #define TPDA_Pn_CR_ENA BIT(0)
>> /* Aggregator port CMB data set element size bit */
>> @@ -19,6 +32,8 @@
>> /* Bits 6 ~ 12 is for atid value */
>> #define TPDA_CR_ATID GENMASK(12, 6)
>> +/* Bits 13 ~ 19 is for mid value */
>> +#define TPDA_CR_MID GENMASK(19, 13)
>> /**
>> * struct tpda_drvdata - specifics associated to an TPDA component
>> @@ -29,6 +44,11 @@
>> * @enable: enable status of the component.
>> * @dsb_esize Record the DSB element size.
>> * @cmb_esize Record the CMB element size.
>> + * @trig_async: Enable/disable cross trigger synchronization
>> sequence interface.
>> + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request
>> interface.
>> + * @trig_freq: Enable/disable cross trigger FREQ packet request
>> interface.
>> + * @freq_ts: Enable/disable the timestamp for all FREQ packets.
>> + * @cmbchan_mode: Configure the CMB/MCMB channel mode.
>> */
>> struct tpda_drvdata {
>> void __iomem *base;
>> @@ -38,6 +58,11 @@ struct tpda_drvdata {
>> u8 atid;
>> u32 dsb_esize;
>> u32 cmb_esize;
>> + bool trig_async;
>> + bool trig_flag_ts;
>> + bool trig_freq;
>> + bool freq_ts;
>> + bool cmbchan_mode;
>> };
>> #endif /* _CORESIGHT_CORESIGHT_TPDA_H */
>>
>
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