On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
IRQ lines out of the 96 available to wire them to the GIC input lines.
Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
drivers/soc/renesas/Kconfig | 4 +
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/rzn1_irqmux.c | 133 ++++++++++++++++++++++++++++++
3 files changed, 138 insertions(+)
create mode 100644 drivers/soc/renesas/rzn1_irqmux.c
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 340a1ff7e92b..71865778b058 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -62,6 +62,7 @@ config ARCH_RZN1
select PM
select PM_GENERIC_DOMAINS
select ARM_AMBA
+ select RZN1_IRQMUX
if ARM && ARCH_RENESAS
@@ -459,6 +460,9 @@ config PWC_RZV2M
config RST_RCAR
bool "Reset Controller support for R-Car" if COMPILE_TEST
+config RZN1_IRQMUX
+ bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST
+
config SYSC_RZ
bool "System controller for RZ SoCs" if COMPILE_TEST
select MFD_SYSCON
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 3bdcc6a395d5..33d44d964d61 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o
# Family
obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o
obj-$(CONFIG_RST_RCAR) += rcar-rst.o
+obj-$(CONFIG_RZN1_IRQMUX) += rzn1_irqmux.o
obj-$(CONFIG_SYSC_RZ) += rz-sysc.o
diff --git a/drivers/soc/renesas/rzn1_irqmux.c b/drivers/soc/renesas/rzn1_irqmux.c
new file mode 100644
index 000000000000..b4b43aa3e496
--- /dev/null
+++ b/drivers/soc/renesas/rzn1_irqmux.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RZ/N1 GPIO Interrupt Multiplexer
+ *
+ * Copyright 2025 Schneider Electric
+ * Author: Herve Codina <herve.codina@bootlin.com>
+ */
+
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/*
+ * Up to 8 output lines are connected to GIC SPI interrupt controller
+ * starting at IRQ 103.
+ */
+#define RZN1_IRQMUX_GIC_SPI_BASE 103
+#define RZN1_IRQMUX_NUM_OUTPUTS 8
+
+static int rzn1_irqmux_parent_args_to_line_index(struct device *dev,
+ const struct of_phandle_args *parent_args)
+{
+ /*
+ * The parent interrupt should be one of the GIC controller.
+ * Three arguments must be provided.
+ * - args[0]: GIC_SPI
+ * - args[1]: The GIC interrupt number
+ * - args[2]: The interrupt flags
+ *
+ * We retrieve the line index based on the GIC interrupt number
+ * provided.
+ */
+
+ if (parent_args->args_count != 3 ||
+ parent_args->args[0] != GIC_SPI) {
+ dev_err(dev, "Invalid interrupt-map item\n");
+ return -EINVAL;
+ }
+
+ if (parent_args->args[1] < RZN1_IRQMUX_GIC_SPI_BASE ||
+ parent_args->args[1] >= RZN1_IRQMUX_GIC_SPI_BASE + RZN1_IRQMUX_NUM_OUTPUTS) {
+ dev_err(dev, "Invalid GIC interrupt %u\n", parent_args->args[1]);
+ return -EINVAL;
+ }
+
+ return parent_args->args[1] - RZN1_IRQMUX_GIC_SPI_BASE;
+}
+
+static int rzn1_irqmux_setup(struct device *dev, struct device_node *np, u32 __iomem *regs)
+{
+ DECLARE_BITMAP(index_done, RZN1_IRQMUX_NUM_OUTPUTS) = {};
+ struct of_imap_parser imap_parser;
+ struct of_imap_item imap_item;
+ int index;
+ int ret;
+ u32 tmp;
+
+ /* We support only #interrupt-cells = <1> and #address-cells = <0> */
+ ret = of_property_read_u32(np, "#interrupt-cells", &tmp);
+ if (ret)
+ return ret;
+ if (tmp != 1)
+ return -EINVAL;
+
+ ret = of_property_read_u32(np, "#address-cells", &tmp);
+ if (ret)
+ return ret;
+ if (tmp != 0)
+ return -EINVAL;
+
+ ret = of_imap_parser_init(&imap_parser, np, &imap_item);
+ if (ret)
+ return ret;
+
+ for_each_of_imap_item(&imap_parser, &imap_item) {
+ index = rzn1_irqmux_parent_args_to_line_index(dev, &imap_item.parent_args);
+ if (index < 0) {
+ of_node_put(imap_item.parent_args.np);
+ return index;
+ }
+
+ if (test_and_set_bit(index, index_done)) {
+ of_node_put(imap_item.parent_args.np);
+ dev_err(dev, "Mux output line already defined\n");
+ return -EINVAL;
+ }
+
+ /*
+ * The child #address-cells is 0 (already checked). The first
+ * value in imap item is the src hwirq.
+ */
+ writel(imap_item.child_imap[0], regs + index);
+ }
+
+ return 0;
+}
+
+static int rzn1_irqmux_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ u32 __iomem *regs;
+
+ regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ return rzn1_irqmux_setup(dev, np, regs);
+}
+
+static const struct of_device_id rzn1_irqmux_of_match[] = {
+ { .compatible = "renesas,rzn1-gpioirqmux", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzn1_irqmux_of_match);
+
+static struct platform_driver rzn1_irqmux_driver = {
+ .probe = rzn1_irqmux_probe,
+ .driver = {
+ .name = "rzn1_irqmux",
+ .of_match_table = rzn1_irqmux_of_match,
+ },
+};
+module_platform_driver(rzn1_irqmux_driver);
+
+MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
+MODULE_DESCRIPTION("Renesas RZ/N1 GPIO IRQ Multiplexer Driver");
+MODULE_LICENSE("GPL");
--
2.51.0Hi Hervé,
On Mon, 27 Oct 2025 at 13:36, Herve Codina (Schneider Electric)
<herve.codina@bootlin.com> wrote:
> On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
> interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
> order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
>
> The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
> IRQ lines out of the 96 available to wire them to the GIC input lines.
>
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
Thanks for your patch!
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -62,6 +62,7 @@ config ARCH_RZN1
> select PM
> select PM_GENERIC_DOMAINS
> select ARM_AMBA
> + select RZN1_IRQMUX
I guess it makes some sense to enable this unconditionally...
But as the GPIO driver it relies on is not enabled automatically,
perhaps
select RZN1_IRQMUX if GPIO_DWAPB
?
>
> if ARM && ARCH_RENESAS
>
> @@ -459,6 +460,9 @@ config PWC_RZV2M
> config RST_RCAR
> bool "Reset Controller support for R-Car" if COMPILE_TEST
>
> +config RZN1_IRQMUX
> + bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST
> +
> config SYSC_RZ
> bool "System controller for RZ SoCs" if COMPILE_TEST
> select MFD_SYSCON
> --- /dev/null
> +++ b/drivers/soc/renesas/rzn1_irqmux.c
> +static int rzn1_irqmux_parent_args_to_line_index(struct device *dev,
> + const struct of_phandle_args *parent_args)
> +{
> + /*
> + * The parent interrupt should be one of the GIC controller.
> + * Three arguments must be provided.
> + * - args[0]: GIC_SPI
> + * - args[1]: The GIC interrupt number
> + * - args[2]: The interrupt flags
> + *
> + * We retrieve the line index based on the GIC interrupt number
> + * provided.
> + */
> +
> + if (parent_args->args_count != 3 ||
> + parent_args->args[0] != GIC_SPI) {
Fits on a single line.
> + dev_err(dev, "Invalid interrupt-map item\n");
> + return -EINVAL;
> + }
> +
> + if (parent_args->args[1] < RZN1_IRQMUX_GIC_SPI_BASE ||
> + parent_args->args[1] >= RZN1_IRQMUX_GIC_SPI_BASE + RZN1_IRQMUX_NUM_OUTPUTS) {
> + dev_err(dev, "Invalid GIC interrupt %u\n", parent_args->args[1]);
> + return -EINVAL;
> + }
> +
> + return parent_args->args[1] - RZN1_IRQMUX_GIC_SPI_BASE;
> +}
> +
> +static int rzn1_irqmux_setup(struct device *dev, struct device_node *np, u32 __iomem *regs)
> +{
> + DECLARE_BITMAP(index_done, RZN1_IRQMUX_NUM_OUTPUTS) = {};
> + struct of_imap_parser imap_parser;
> + struct of_imap_item imap_item;
> + int index;
> + int ret;
> + u32 tmp;
> +
> + /* We support only #interrupt-cells = <1> and #address-cells = <0> */
> + ret = of_property_read_u32(np, "#interrupt-cells", &tmp);
> + if (ret)
> + return ret;
> + if (tmp != 1)
> + return -EINVAL;
> +
> + ret = of_property_read_u32(np, "#address-cells", &tmp);
> + if (ret)
> + return ret;
> + if (tmp != 0)
> + return -EINVAL;
> +
> + ret = of_imap_parser_init(&imap_parser, np, &imap_item);
> + if (ret)
> + return ret;
> +
> + for_each_of_imap_item(&imap_parser, &imap_item) {
> + index = rzn1_irqmux_parent_args_to_line_index(dev, &imap_item.parent_args);
> + if (index < 0) {
> + of_node_put(imap_item.parent_args.np);
> + return index;
> + }
> +
> + if (test_and_set_bit(index, index_done)) {
> + of_node_put(imap_item.parent_args.np);
> + dev_err(dev, "Mux output line already defined\n");
Perhaps print the actual index? E.g.
dev_err(dev, "Duplicate GIC_SPI interrupt %u in interrupt-map\n",
RZN1_IRQMUX_GIC_SPI_BASE + index);
Hmm, having to add the base again would be a reason to let
rzn1_irqmux_parent_args_to_line_index() return the actual GIC interrupt
number instead...
> + return -EINVAL;
> + }
> +
> + /*
> + * The child #address-cells is 0 (already checked). The first
> + * value in imap item is the src hwirq.
> + */
> + writel(imap_item.child_imap[0], regs + index);
> + }
> +
> + return 0;
> +}
> +
> +static int rzn1_irqmux_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + u32 __iomem *regs;
> +
> + regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(regs))
> + return PTR_ERR(regs);
> +
> + return rzn1_irqmux_setup(dev, np, regs);
As Wolfram already pointed out, this function looks a bit shallow.
> +}
Nothing critical, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Herve,
On Mon, Oct 27, 2025 at 01:35:59PM +0100, Herve Codina (Schneider Electric) wrote:
> On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
> interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
> order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
>
> The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
> IRQ lines out of the 96 available to wire them to the GIC input lines.
>
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
Good news first:
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
I can access GPIO LEDs on my board and PHY interrupts also work.
> + if (parent_args->args[1] < RZN1_IRQMUX_GIC_SPI_BASE ||
> + parent_args->args[1] >= RZN1_IRQMUX_GIC_SPI_BASE + RZN1_IRQMUX_NUM_OUTPUTS) {
> + dev_err(dev, "Invalid GIC interrupt %u\n", parent_args->args[1]);
> + return -EINVAL;
> + }
I really like this solution. I think I suggested it before but can't
recall the details. And it is not worth digging it up again. Looks good,
works, perfect.
...
> +static int rzn1_irqmux_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + u32 __iomem *regs;
> +
> + regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(regs))
> + return PTR_ERR(regs);
> +
> + return rzn1_irqmux_setup(dev, np, regs);
The only super minor thing is that we could fold rzn1_irqmux_setup()
into probe() according to my taste. But I am also fine as is. Looking
really forward to see this series finally going upstream.
Thanks again for your work on this!
Wolfram
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