cstate support for CWF, LNL and PTL

[PATCH RESEND 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

Posted by Zide Chen 3 months, 2 weeks ago

Clearwater Forest is based on the Darkmont Atom microarchitecture.
From the perspective of C-state residency profiling, it supports the
same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6.

Please note that the C1E residency counter can only be read via PMT,
not MSR. Therefore, tools relying on the perf_event framework cannot
access the C1E residency.

Cc: Artem Bityutskiy <artem.bityutskiy@intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
---
 arch/x86/events/intel/cstate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index ec753e39b007..a5f2e0be2337 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -628,6 +628,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_MATCH_VFM(INTEL_ATOM_GRACEMONT,	&adl_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X,	&srf_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_CRESTMONT,	&grr_cstates),
+	X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X,	&srf_cstates),
 
 	X86_MATCH_VFM(INTEL_ICELAKE_L,		&icl_cstates),
 	X86_MATCH_VFM(INTEL_ICELAKE,		&icl_cstates),
-- 
2.51.1

Re: [PATCH RESEND 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

Posted by Ingo Molnar 3 months, 1 week ago

* Zide Chen <zide.chen@intel.com> wrote:

> Clearwater Forest is based on the Darkmont Atom microarchitecture.
> From the perspective of C-state residency profiling, it supports the
> same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6.
> 
> Please note that the C1E residency counter can only be read via PMT,
> not MSR. Therefore, tools relying on the perf_event framework cannot
> access the C1E residency.
> 
> Cc: Artem Bityutskiy <artem.bityutskiy@intel.com>
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
> Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
> Signed-off-by: Zide Chen <zide.chen@intel.com>

So, this is not a valid SOB chain: primary author should be the first 
SOB, or if it was co-developed, it should have the proper 
Co-developed-by tags.

Here I can see two possibilities:

(1) if Zhenyu Wang was the primary author, and Zide Chen reviewed, 
    tested and submitted it upstream, then:


  | From: Zide Chen <zide.chen@intel.com>
  | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

    From: Zhenyu Wang <zhenyuw.linux@gmail.com>
    ...

    Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
    Signed-off-by: Zide Chen <zide.chen@intel.com>

(I.e. add the extra From line as the first line of the changelog.)

(2) if it was co-developed, with Zhenyu Wang and Zide Chen having each 
    written unique lines of code of their own that finally resulted in 
    this submission, then:

  | From: Zide Chen <zide.chen@intel.com>
  | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

    ...

    Co-developed-by: Zide Chen <zide.chen@intel.com>
    Signed-off-by: Zide Chen <zide.chen@intel.com>
    Co-developed-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
    Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>

Which one was it? :-)

Thanks,

	Ingo

Re: [PATCH RESEND 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

Posted by Chen, Zide 3 months, 1 week ago


On 10/30/2025 2:09 AM, Ingo Molnar wrote:
> 
> * Zide Chen <zide.chen@intel.com> wrote:
> 
>> Clearwater Forest is based on the Darkmont Atom microarchitecture.
>> From the perspective of C-state residency profiling, it supports the
>> same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6.
>>
>> Please note that the C1E residency counter can only be read via PMT,
>> not MSR. Therefore, tools relying on the perf_event framework cannot
>> access the C1E residency.
>>
>> Cc: Artem Bityutskiy <artem.bityutskiy@intel.com>
>> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
>> Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
>> Signed-off-by: Zide Chen <zide.chen@intel.com>
> 
> So, this is not a valid SOB chain: primary author should be the first 
> SOB, or if it was co-developed, it should have the proper 
> Co-developed-by tags.
> 
> Here I can see two possibilities:
> 
> (1) if Zhenyu Wang was the primary author, and Zide Chen reviewed, 
>     tested and submitted it upstream, then:
> 
> 
>   | From: Zide Chen <zide.chen@intel.com>
>   | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support
> 
>     From: Zhenyu Wang <zhenyuw.linux@gmail.com>
>     ...
> 
>     Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
>     Signed-off-by: Zide Chen <zide.chen@intel.com>
> 
> (I.e. add the extra From line as the first line of the changelog.)

Yes, that is the case.
Thank you very much for pointing this out! I will pay extra attention to
the SoB chain going forward.


> (2) if it was co-developed, with Zhenyu Wang and Zide Chen having each 
>     written unique lines of code of their own that finally resulted in 
>     this submission, then:
> 
>   | From: Zide Chen <zide.chen@intel.com>
>   | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support
> 
>     ...
> 
>     Co-developed-by: Zide Chen <zide.chen@intel.com>
>     Signed-off-by: Zide Chen <zide.chen@intel.com>
>     Co-developed-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
>     Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
> 
> Which one was it? :-)
> 
> Thanks,
> 
> 	Ingo

[tip: perf/core] perf/x86/intel/cstate: Add Clearwater Forest support

Posted by tip-bot2 for Zide Chen 3 months, 1 week ago

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     e39b82f6cb0526c551d4651ba6d286b6b1f9e9c3
Gitweb:        https://git.kernel.org/tip/e39b82f6cb0526c551d4651ba6d286b6b1f9e9c3
Author:        Zide Chen <zide.chen@intel.com>
AuthorDate:    Thu, 23 Oct 2025 15:37:51 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Wed, 29 Oct 2025 10:29:53 +01:00

perf/x86/intel/cstate: Add Clearwater Forest support

Clearwater Forest is based on the Darkmont Atom microarchitecture.
>From the perspective of C-state residency profiling, it supports the
same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6.

Please note that the C1E residency counter can only be read via PMT,
not MSR. Therefore, tools relying on the perf_event framework cannot
access the C1E residency.

Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20251023223754.1743928-2-zide.chen@intel.com
---
 arch/x86/events/intel/cstate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index ec753e3..a5f2e0b 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -628,6 +628,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_MATCH_VFM(INTEL_ATOM_GRACEMONT,	&adl_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X,	&srf_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_CRESTMONT,	&grr_cstates),
+	X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X,	&srf_cstates),
 
 	X86_MATCH_VFM(INTEL_ICELAKE_L,		&icl_cstates),
 	X86_MATCH_VFM(INTEL_ICELAKE,		&icl_cstates),