From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add FCPV and VSPD nodes to RZ/V2H(P) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 40b15f1db930..47b3502846f6 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -1303,6 +1303,30 @@ queue3 {
};
};
};
+
+ fcpvd: fcp@16470000 {
+ compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv";
+ reg = <0 0x16470000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ };
+
+ vspd: vsp@16480000 {
+ compatible = "renesas,r9a09g057-vsp2", "renesas,r9a07g044-vsp2";
+ reg = <0 0x16480000 0 0x10000>;
+ interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ renesas,fcp = <&fcpvd>;
+ };
};
stmmac_axi_setup: stmmac-axi-config {
--
2.43.0