Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs expose the
temperature calibration via SMC SIP and do not have a reset for the
TSU peripheral, and use different minimum and maximum temperature values
compared to RZ/G3E.

Although the calibration data is stored in an OTP memory, the OTP itself
is not memory-mapped, and instead, access to it is done through an OTP
controller. The OTP controller is only accessible from the secure world,
but the temperature calibration data stored in the OTP is exposed via
SMC.

Cosmin Tanislav (10):
  clk: renesas: r9a09g077: add TSU module clock
  thermal: renesas: rzg3e: make reset optional
  thermal: renesas: rzg3e: make min and max temperature per-chip
  thermal: renesas: rzg3e: make calibration value retrieval per-chip
  dt-bindings: thermal: r9a09g047-tsu: document RZ/T2H and RZ/N2H
  thermal: renesas: rzg3e: add support for RZ/T2H and RZ/N2H
  arm64: dts: renesas: r9a09g077: add OPP table
  arm64: dts: renesas: r9a09g087: add OPP table
  arm64: dts: renesas: r9a09g077: add TSU and thermal zones support
  arm64: dts: renesas: r9a09g087: add TSU and thermal zones support

 .../thermal/renesas,r9a09g047-tsu.yaml        |  22 ++-
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi    |  65 +++++++++
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi    |  65 +++++++++
 drivers/clk/renesas/r9a09g077-cpg.c           |   1 +
 drivers/thermal/renesas/rzg3e_thermal.c       | 125 ++++++++++++------
 5 files changed, 232 insertions(+), 46 deletions(-)

-- 
2.51.1.dirty