From: Guoniu Zhou <guoniu.zhou@nxp.com>
The CSI-2 receiver in the i.MX8ULP is almost identical to the version
present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk
clock as the input clock for its APB interface of Control and Status
register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and
increase maxItems of Clocks (clock-names) to 4 from 3. And keep the
same restriction for existing compatible.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
---
.../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 41 ++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
index 3389bab266a9adbda313c8ad795b998641df12f3..da3978da1cab75292ada3f24837443f7f4ab6418 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
@@ -20,6 +20,7 @@ properties:
- enum:
- fsl,imx8mq-mipi-csi2
- fsl,imx8qxp-mipi-csi2
+ - fsl,imx8ulp-mipi-csi2
- items:
- const: fsl,imx8qm-mipi-csi2
- const: fsl,imx8qxp-mipi-csi2
@@ -39,12 +40,16 @@ properties:
clock that the RX DPHY receives.
- description: ui is the pixel clock (phy_ref up to 333Mhz).
See the reference manual for details.
+ - description: pclk is clock for csr APB interface.
+ minItems: 3
clock-names:
items:
- const: core
- const: esc
- const: ui
+ - const: pclk
+ minItems: 3
power-domains:
maxItems: 1
@@ -130,19 +135,51 @@ allOf:
compatible:
contains:
enum:
- - fsl,imx8qxp-mipi-csi2
+ - fsl,imx8ulp-mipi-csi2
+ then:
+ properties:
+ reg:
+ minItems: 2
+ resets:
+ minItems: 2
+ maxItems: 2
+ clocks:
+ minItems: 4
+ clock-names:
+ minItems: 4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qxp-mipi-csi2
then:
properties:
reg:
minItems: 2
resets:
maxItems: 1
- else:
+ clocks:
+ maxItems: 3
+ clock-names:
+ maxItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mq-mipi-csi2
+ then:
properties:
reg:
maxItems: 1
resets:
minItems: 3
+ clocks:
+ maxItems: 3
+ clock-names:
+ maxItems: 3
required:
- fsl,mipi-phy-gpr
--
2.34.1Hi Guoniu, On Thu, Oct 23, 2025 at 05:19:42PM +0800, Guoniu Zhou wrote: > From: Guoniu Zhou <guoniu.zhou@nxp.com> > > The CSI-2 receiver in the i.MX8ULP is almost identical to the version > present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk > clock as the input clock for its APB interface of Control and Status > register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and > increase maxItems of Clocks (clock-names) to 4 from 3. And keep the > same restriction for existing compatible. > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> > --- > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 41 ++++++++++++++++++++-- > 1 file changed, 39 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > index 3389bab266a9adbda313c8ad795b998641df12f3..da3978da1cab75292ada3f24837443f7f4ab6418 100644 > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > @@ -20,6 +20,7 @@ properties: > - enum: > - fsl,imx8mq-mipi-csi2 > - fsl,imx8qxp-mipi-csi2 > + - fsl,imx8ulp-mipi-csi2 > - items: > - const: fsl,imx8qm-mipi-csi2 > - const: fsl,imx8qxp-mipi-csi2 > @@ -39,12 +40,16 @@ properties: > clock that the RX DPHY receives. > - description: ui is the pixel clock (phy_ref up to 333Mhz). > See the reference manual for details. > + - description: pclk is clock for csr APB interface. > + minItems: 3 > > clock-names: > items: > - const: core > - const: esc > - const: ui > + - const: pclk > + minItems: 3 > > power-domains: > maxItems: 1 > @@ -130,19 +135,51 @@ allOf: > compatible: > contains: > enum: > - - fsl,imx8qxp-mipi-csi2 > + - fsl,imx8ulp-mipi-csi2 > + then: > + properties: > + reg: > + minItems: 2 > + resets: > + minItems: 2 > + maxItems: 2 > + clocks: > + minItems: 4 > + clock-names: > + minItems: 4 Do we need the clock-names constraint ? The DT schemas will enforce that clocks and clock-names always have the same number of elements. > + > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx8qxp-mipi-csi2 > then: > properties: > reg: > minItems: 2 > resets: > maxItems: 1 > - else: > + clocks: > + maxItems: 3 > + clock-names: > + maxItems: 3 > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8mq-mipi-csi2 > + then: > properties: > reg: > maxItems: 1 > resets: > minItems: 3 > + clocks: > + maxItems: 3 > + clock-names: > + maxItems: 3 > required: > - fsl,mipi-phy-gpr > Could you please sort those conditional blocks by alphabetical order of the compatible strings ? -- Regards, Laurent Pinchart
On Mon, Oct 27, 2025 at 02:05:37AM +0200, Laurent Pinchart wrote:
> Hi Guoniu,
>
> On Thu, Oct 23, 2025 at 05:19:42PM +0800, Guoniu Zhou wrote:
> > From: Guoniu Zhou <guoniu.zhou@nxp.com>
> >
> > The CSI-2 receiver in the i.MX8ULP is almost identical to the version
> > present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk
> > clock as the input clock for its APB interface of Control and Status
> > register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and
> > increase maxItems of Clocks (clock-names) to 4 from 3. And keep the
> > same restriction for existing compatible.
> >
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
> > ---
> > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 41 ++++++++++++++++++++--
> > 1 file changed, 39 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> > index 3389bab266a9adbda313c8ad795b998641df12f3..da3978da1cab75292ada3f24837443f7f4ab6418 100644
> > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> > @@ -20,6 +20,7 @@ properties:
> > - enum:
> > - fsl,imx8mq-mipi-csi2
> > - fsl,imx8qxp-mipi-csi2
> > + - fsl,imx8ulp-mipi-csi2
> > - items:
> > - const: fsl,imx8qm-mipi-csi2
> > - const: fsl,imx8qxp-mipi-csi2
> > @@ -39,12 +40,16 @@ properties:
> > clock that the RX DPHY receives.
> > - description: ui is the pixel clock (phy_ref up to 333Mhz).
> > See the reference manual for details.
> > + - description: pclk is clock for csr APB interface.
> > + minItems: 3
> >
> > clock-names:
> > items:
> > - const: core
> > - const: esc
> > - const: ui
> > + - const: pclk
> > + minItems: 3
> >
> > power-domains:
> > maxItems: 1
> > @@ -130,19 +135,51 @@ allOf:
> > compatible:
> > contains:
> > enum:
> > - - fsl,imx8qxp-mipi-csi2
> > + - fsl,imx8ulp-mipi-csi2
> > + then:
> > + properties:
> > + reg:
> > + minItems: 2
> > + resets:
> > + minItems: 2
> > + maxItems: 2
> > + clocks:
> > + minItems: 4
> > + clock-names:
> > + minItems: 4
>
> Do we need the clock-names constraint ? The DT schemas will enforce that
> clocks and clock-names always have the same number of elements.
>
clock-names list already restrict at top section
clock-names:
items:
- const: core
- const: esc
- const: ui
- const: pclk
minItems: 3
Here just restrict need 4 clocks, instead 3 clock for fsl,imx8ulp-mipi-csi2
Frank
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: fsl,imx8qxp-mipi-csi2
> > then:
> > properties:
> > reg:
> > minItems: 2
> > resets:
> > maxItems: 1
> > - else:
> > + clocks:
> > + maxItems: 3
> > + clock-names:
> > + maxItems: 3
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - fsl,imx8mq-mipi-csi2
> > + then:
> > properties:
> > reg:
> > maxItems: 1
> > resets:
> > minItems: 3
> > + clocks:
> > + maxItems: 3
> > + clock-names:
> > + maxItems: 3
> > required:
> > - fsl,mipi-phy-gpr
> >
>
> Could you please sort those conditional blocks by alphabetical order of
> the compatible strings ?
>
> --
> Regards,
>
> Laurent Pinchart
On Tue, Nov 11, 2025 at 03:47:51PM -0500, Frank Li wrote: > On Mon, Oct 27, 2025 at 02:05:37AM +0200, Laurent Pinchart wrote: > > On Thu, Oct 23, 2025 at 05:19:42PM +0800, Guoniu Zhou wrote: > > > From: Guoniu Zhou <guoniu.zhou@nxp.com> > > > > > > The CSI-2 receiver in the i.MX8ULP is almost identical to the version > > > present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk > > > clock as the input clock for its APB interface of Control and Status > > > register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and > > > increase maxItems of Clocks (clock-names) to 4 from 3. And keep the > > > same restriction for existing compatible. > > > > > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > > > Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> > > > --- > > > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 41 ++++++++++++++++++++-- > > > 1 file changed, 39 insertions(+), 2 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > index 3389bab266a9adbda313c8ad795b998641df12f3..da3978da1cab75292ada3f24837443f7f4ab6418 100644 > > > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > @@ -20,6 +20,7 @@ properties: > > > - enum: > > > - fsl,imx8mq-mipi-csi2 > > > - fsl,imx8qxp-mipi-csi2 > > > + - fsl,imx8ulp-mipi-csi2 > > > - items: > > > - const: fsl,imx8qm-mipi-csi2 > > > - const: fsl,imx8qxp-mipi-csi2 > > > @@ -39,12 +40,16 @@ properties: > > > clock that the RX DPHY receives. > > > - description: ui is the pixel clock (phy_ref up to 333Mhz). > > > See the reference manual for details. > > > + - description: pclk is clock for csr APB interface. > > > + minItems: 3 > > > > > > clock-names: > > > items: > > > - const: core > > > - const: esc > > > - const: ui > > > + - const: pclk > > > + minItems: 3 > > > > > > power-domains: > > > maxItems: 1 > > > @@ -130,19 +135,51 @@ allOf: > > > compatible: > > > contains: > > > enum: > > > - - fsl,imx8qxp-mipi-csi2 > > > + - fsl,imx8ulp-mipi-csi2 > > > + then: > > > + properties: > > > + reg: > > > + minItems: 2 > > > + resets: > > > + minItems: 2 > > > + maxItems: 2 > > > + clocks: > > > + minItems: 4 > > > + clock-names: > > > + minItems: 4 > > > > Do we need the clock-names constraint ? The DT schemas will enforce that > > clocks and clock-names always have the same number of elements. > > clock-names list already restrict at top section > > clock-names: > items: > - const: core > - const: esc > - const: ui > - const: pclk > minItems: 3 > > Here just restrict need 4 clocks, instead 3 clock for fsl,imx8ulp-mipi-csi2 I understand that. My point was that the dt-schema will always verify that the number of clocks items is equal to the number of clock-names items. That's a constraint enforced by the core schemas. As clocks: minItems is set to 4, the clock-names: minItems constraint is redundant. > > > + > > > + - if: > > > + properties: > > > + compatible: > > > + contains: > > > + const: fsl,imx8qxp-mipi-csi2 > > > then: > > > properties: > > > reg: > > > minItems: 2 > > > resets: > > > maxItems: 1 > > > - else: > > > + clocks: > > > + maxItems: 3 > > > + clock-names: > > > + maxItems: 3 > > > + > > > + - if: > > > + properties: > > > + compatible: > > > + contains: > > > + enum: > > > + - fsl,imx8mq-mipi-csi2 > > > + then: > > > properties: > > > reg: > > > maxItems: 1 > > > resets: > > > minItems: 3 > > > + clocks: > > > + maxItems: 3 > > > + clock-names: > > > + maxItems: 3 > > > required: > > > - fsl,mipi-phy-gpr > > > > > > > Could you please sort those conditional blocks by alphabetical order of > > the compatible strings ? -- Regards, Laurent Pinchart
On Tue, Nov 11, 2025 at 11:10:25PM +0200, Laurent Pinchart wrote: > On Tue, Nov 11, 2025 at 03:47:51PM -0500, Frank Li wrote: > > On Mon, Oct 27, 2025 at 02:05:37AM +0200, Laurent Pinchart wrote: > > > On Thu, Oct 23, 2025 at 05:19:42PM +0800, Guoniu Zhou wrote: > > > > From: Guoniu Zhou <guoniu.zhou@nxp.com> > > > > > > > > The CSI-2 receiver in the i.MX8ULP is almost identical to the version > > > > present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk > > > > clock as the input clock for its APB interface of Control and Status > > > > register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and > > > > increase maxItems of Clocks (clock-names) to 4 from 3. And keep the > > > > same restriction for existing compatible. > > > > > > > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > > > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > > > > Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> > > > > --- > > > > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 41 ++++++++++++++++++++-- > > > > 1 file changed, 39 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > > index 3389bab266a9adbda313c8ad795b998641df12f3..da3978da1cab75292ada3f24837443f7f4ab6418 100644 > > > > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > > @@ -20,6 +20,7 @@ properties: > > > > - enum: > > > > - fsl,imx8mq-mipi-csi2 > > > > - fsl,imx8qxp-mipi-csi2 > > > > + - fsl,imx8ulp-mipi-csi2 > > > > - items: > > > > - const: fsl,imx8qm-mipi-csi2 > > > > - const: fsl,imx8qxp-mipi-csi2 > > > > @@ -39,12 +40,16 @@ properties: > > > > clock that the RX DPHY receives. > > > > - description: ui is the pixel clock (phy_ref up to 333Mhz). > > > > See the reference manual for details. > > > > + - description: pclk is clock for csr APB interface. > > > > + minItems: 3 > > > > > > > > clock-names: > > > > items: > > > > - const: core > > > > - const: esc > > > > - const: ui > > > > + - const: pclk > > > > + minItems: 3 > > > > > > > > power-domains: > > > > maxItems: 1 > > > > @@ -130,19 +135,51 @@ allOf: > > > > compatible: > > > > contains: > > > > enum: > > > > - - fsl,imx8qxp-mipi-csi2 > > > > + - fsl,imx8ulp-mipi-csi2 > > > > + then: > > > > + properties: > > > > + reg: > > > > + minItems: 2 > > > > + resets: > > > > + minItems: 2 > > > > + maxItems: 2 > > > > + clocks: > > > > + minItems: 4 > > > > + clock-names: > > > > + minItems: 4 > > > > > > Do we need the clock-names constraint ? The DT schemas will enforce that > > > clocks and clock-names always have the same number of elements. > > > > clock-names list already restrict at top section > > > > clock-names: > > items: > > - const: core > > - const: esc > > - const: ui > > - const: pclk > > minItems: 3 > > > > Here just restrict need 4 clocks, instead 3 clock for fsl,imx8ulp-mipi-csi2 > > I understand that. My point was that the dt-schema will always verify > that the number of clocks items is equal to the number of clock-names > items. That's a constraint enforced by the core schemas. As > clocks: minItems is set to 4, the clock-names: minItems constraint is > redundant. I am not sure when have such features. Previous comments from Rob require clocks and clock-names keep the same at binding yaml. https://lore.kernel.org/linux-devicetree/20251031000012.GA466250-robh@kernel.org/ Rob have not said that clock-names can be removed. Do you have any thread, which inidicate we only need limit clocks at if-else branch? I also have not found related commit at https://github.com/devicetree-org/dt-schema.git Frank > > > > > + > > > > + - if: > > > > + properties: > > > > + compatible: > > > > + contains: > > > > + const: fsl,imx8qxp-mipi-csi2 > > > > then: > > > > properties: > > > > reg: > > > > minItems: 2 > > > > resets: > > > > maxItems: 1 > > > > - else: > > > > + clocks: > > > > + maxItems: 3 > > > > + clock-names: > > > > + maxItems: 3 > > > > + > > > > + - if: > > > > + properties: > > > > + compatible: > > > > + contains: > > > > + enum: > > > > + - fsl,imx8mq-mipi-csi2 > > > > + then: > > > > properties: > > > > reg: > > > > maxItems: 1 > > > > resets: > > > > minItems: 3 > > > > + clocks: > > > > + maxItems: 3 > > > > + clock-names: > > > > + maxItems: 3 > > > > required: > > > > - fsl,mipi-phy-gpr > > > > > > > > > > Could you please sort those conditional blocks by alphabetical order of > > > the compatible strings ? > > -- > Regards, > > Laurent Pinchart
On Tue, Nov 11, 2025 at 05:06:02PM -0500, Frank Li wrote: > On Tue, Nov 11, 2025 at 11:10:25PM +0200, Laurent Pinchart wrote: > > On Tue, Nov 11, 2025 at 03:47:51PM -0500, Frank Li wrote: > > > On Mon, Oct 27, 2025 at 02:05:37AM +0200, Laurent Pinchart wrote: > > > > On Thu, Oct 23, 2025 at 05:19:42PM +0800, Guoniu Zhou wrote: > > > > > From: Guoniu Zhou <guoniu.zhou@nxp.com> > > > > > > > > > > The CSI-2 receiver in the i.MX8ULP is almost identical to the version > > > > > present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk > > > > > clock as the input clock for its APB interface of Control and Status > > > > > register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and > > > > > increase maxItems of Clocks (clock-names) to 4 from 3. And keep the > > > > > same restriction for existing compatible. > > > > > > > > > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > > > > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > > > > > Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> > > > > > --- > > > > > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 41 ++++++++++++++++++++-- > > > > > 1 file changed, 39 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > > > index 3389bab266a9adbda313c8ad795b998641df12f3..da3978da1cab75292ada3f24837443f7f4ab6418 100644 > > > > > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > > > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > > > > @@ -20,6 +20,7 @@ properties: > > > > > - enum: > > > > > - fsl,imx8mq-mipi-csi2 > > > > > - fsl,imx8qxp-mipi-csi2 > > > > > + - fsl,imx8ulp-mipi-csi2 > > > > > - items: > > > > > - const: fsl,imx8qm-mipi-csi2 > > > > > - const: fsl,imx8qxp-mipi-csi2 > > > > > @@ -39,12 +40,16 @@ properties: > > > > > clock that the RX DPHY receives. > > > > > - description: ui is the pixel clock (phy_ref up to 333Mhz). > > > > > See the reference manual for details. > > > > > + - description: pclk is clock for csr APB interface. > > > > > + minItems: 3 > > > > > > > > > > clock-names: > > > > > items: > > > > > - const: core > > > > > - const: esc > > > > > - const: ui > > > > > + - const: pclk > > > > > + minItems: 3 > > > > > > > > > > power-domains: > > > > > maxItems: 1 > > > > > @@ -130,19 +135,51 @@ allOf: > > > > > compatible: > > > > > contains: > > > > > enum: > > > > > - - fsl,imx8qxp-mipi-csi2 > > > > > + - fsl,imx8ulp-mipi-csi2 > > > > > + then: > > > > > + properties: > > > > > + reg: > > > > > + minItems: 2 > > > > > + resets: > > > > > + minItems: 2 > > > > > + maxItems: 2 > > > > > + clocks: > > > > > + minItems: 4 > > > > > + clock-names: > > > > > + minItems: 4 > > > > > > > > Do we need the clock-names constraint ? The DT schemas will enforce that > > > > clocks and clock-names always have the same number of elements. > > > > > > clock-names list already restrict at top section > > > > > > clock-names: > > > items: > > > - const: core > > > - const: esc > > > - const: ui > > > - const: pclk > > > minItems: 3 > > > > > > Here just restrict need 4 clocks, instead 3 clock for fsl,imx8ulp-mipi-csi2 > > > > I understand that. My point was that the dt-schema will always verify > > that the number of clocks items is equal to the number of clock-names > > items. That's a constraint enforced by the core schemas. As > > clocks: minItems is set to 4, the clock-names: minItems constraint is > > redundant. > > I am not sure when have such features. Previous comments from Rob require > clocks and clock-names keep the same at binding yaml. > > https://lore.kernel.org/linux-devicetree/20251031000012.GA466250-robh@kernel.org/ > > Rob have not said that clock-names can be removed. > > Do you have any thread, which inidicate we only need limit clocks at > if-else branch? > > I also have not found related commit at > https://github.com/devicetree-org/dt-schema.git I think you're right. There are dependencies between clock-names and clocks described in the DT schemas, but I don't see any automatic dependency regarding the number of items. I seem to have dreamt this :-/ Sorry about the noise. > > > > > + > > > > > + - if: > > > > > + properties: > > > > > + compatible: > > > > > + contains: > > > > > + const: fsl,imx8qxp-mipi-csi2 > > > > > then: > > > > > properties: > > > > > reg: > > > > > minItems: 2 > > > > > resets: > > > > > maxItems: 1 > > > > > - else: > > > > > + clocks: > > > > > + maxItems: 3 > > > > > + clock-names: > > > > > + maxItems: 3 > > > > > + > > > > > + - if: > > > > > + properties: > > > > > + compatible: > > > > > + contains: > > > > > + enum: > > > > > + - fsl,imx8mq-mipi-csi2 > > > > > + then: > > > > > properties: > > > > > reg: > > > > > maxItems: 1 > > > > > resets: > > > > > minItems: 3 > > > > > + clocks: > > > > > + maxItems: 3 > > > > > + clock-names: > > > > > + maxItems: 3 > > > > > required: > > > > > - fsl,mipi-phy-gpr > > > > > > > > > > > > > Could you please sort those conditional blocks by alphabetical order of > > > > the compatible strings ? -- Regards, Laurent Pinchart
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