Hi,

This series extends the versaclock3 driver to support the internal
freerunning 32.768 kHz clock, which is used on the RZ/V2H SoC as RTC
counter clock. It also adds the dts node for the RZ/V2H EVK.

Best regards,
Ovidiu

Ovidiu Panait (4):
  clk: versaclock3: Remove unused SE2 clock select macro
  clk: versaclock3: Use clk_parent_data arrays for clk_mux
  clk: versaclock3: Add freerunning 32.768kHz clock support
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock
    generator node

 .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    |  25 ++++
 drivers/clk/clk-versaclock3.c                 | 126 +++++++++++++-----
 2 files changed, 120 insertions(+), 31 deletions(-)

-- 
2.51.0

Hi Geert,

On 10/21/25 8:53 PM, Ovidiu Panait wrote:
> Hi,
> 
> This series extends the versaclock3 driver to support the internal
> freerunning 32.768 kHz clock, which is used on the RZ/V2H SoC as RTC
> counter clock. It also adds the dts node for the RZ/V2H EVK.
> 

I wanted to check whether you had a chance to look at this patchset.
Please let me know if you have any comments/feedback. Thanks!

Ovidiu

> Best regards,
> Ovidiu
> 
> Ovidiu Panait (4):
>   clk: versaclock3: Remove unused SE2 clock select macro
>   clk: versaclock3: Use clk_parent_data arrays for clk_mux
>   clk: versaclock3: Add freerunning 32.768kHz clock support
>   arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock
>     generator node
> 
>  .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    |  25 ++++
>  drivers/clk/clk-versaclock3.c                 | 126 +++++++++++++-----
>  2 files changed, 120 insertions(+), 31 deletions(-)
>