Dne ponedeljek, 20. oktober 2025 ob 19:10:51 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):
> The "bus-r-dma" clock in the A523's PRCM clock controller is also
> referred to as "DMA_CLKEN_SW" or "DMA ADB400 gating". It is unclear how
> this ties into the DMA controller MBUS clock gate; however if the clock
> is not enabled, the DMA controller in the MCU block will fail to access
> DRAM, even failing to retrieve the DMA descriptors.
>
> Mark this clock as critical. This sort of mirrors what is done for the
> main DMA controller's MBUS clock, which has a separate toggle that is
> currently left out of the main clock controller driver.
>
> Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
> Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
> ---
> drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
> index 70ce0ca0cb7d..fdcdcccd0939 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
> @@ -121,7 +121,7 @@ static SUNXI_CCU_GATE_HW(bus_r_ir_rx_clk, "bus-r-ir-rx",
> &r_apb0_clk.common.hw, 0x1cc, BIT(0), 0);
>
> static SUNXI_CCU_GATE_HW(bus_r_dma_clk, "bus-r-dma",
> - &r_apb0_clk.common.hw, 0x1dc, BIT(0), 0);
> + &r_apb0_clk.common.hw, 0x1dc, BIT(0), CLK_IS_CRITICAL);
> static SUNXI_CCU_GATE_HW(bus_r_rtc_clk, "bus-r-rtc",
> &r_apb0_clk.common.hw, 0x20c, BIT(0), 0);
> static SUNXI_CCU_GATE_HW(bus_r_cpucfg_clk, "bus-r-cpucfg",
>