The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI.
It allows a debugger to send to trigger events to a processor or to send
a trigger event to one or more processors when a trigger event occurs on
another processor on the same SoC, or even between SoCs.

QCOM extended CTI supports up to 128 triggers. And some of the register
offsets are changed.

The commands to configure CTI triggers are the same as ARM's CTI.

Changes in v5:
1. Move common part in qcom-cti.h to coresight-cti.h.
2. Convert trigger usage fields to dynamic bitmaps and arrays.
3. Fix holes in struct cti_config to save some space.
4. Revert the previous changes related to the claim tag in
   cti_enable/disable_hw.
Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/

Changes in v4:
1. Read the DEVARCH registers to identify Qualcomm CTI.
2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and
coresight_cti_reg_store() functions accordingly.
3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h.
Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/

Changes in v3:
1. Rename is_extended_cti() to of_is_extended_cti().
2. Add the missing 'i' when write the CTI trigger registers.
3. Convert the multi-line output in sysfs to single line.
4. Initialize offset arrays using designated initializer.
Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/

Changes in V2:
1. Add enum for compatible items.
2. Move offset arrays to coresight-cti-core

Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
---
Yingchao Deng (2):
      coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays
      coresight: cti: Add Qualcomm extended CTI support

 drivers/hwtracing/coresight/coresight-cti-core.c   | 144 +++++++++++++---
 .../hwtracing/coresight/coresight-cti-platform.c   |  16 +-
 drivers/hwtracing/coresight/coresight-cti-sysfs.c  | 184 +++++++++++++++------
 drivers/hwtracing/coresight/coresight-cti.h        |  60 ++++++-
 drivers/hwtracing/coresight/qcom-cti.h             |  29 ++++
 5 files changed, 346 insertions(+), 87 deletions(-)
---
base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229
change-id: 20251016-extended_cti-2a426c8894b1

Best regards,
-- 
Yingchao Deng <yingchao.deng@oss.qualcomm.com>

Hi,

This set is looking good now and appears to be getting close to being ready.

There are a few minor issues in the second patch and a few items that
need to be confirmed.
1) I note that you removed the code to prevent calling claim/disclaim.
Does this mean that you confirm that you have tested the patch update
for claim tags I posted works on your system?
2) In patch 2 I made some comments in regard to ARCH values - please
confirm that these are accurate and have been tested as working on
your system
3) As mentioned in the comments to patch 2 - you need to update the
docs for the new sysfs selection file you have added

Thanks and Regards

Mike

On Mon, 20 Oct 2025 at 08:12, Yingchao Deng
<yingchao.deng@oss.qualcomm.com> wrote:
>
> The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI.
> It allows a debugger to send to trigger events to a processor or to send
> a trigger event to one or more processors when a trigger event occurs on
> another processor on the same SoC, or even between SoCs.
>
> QCOM extended CTI supports up to 128 triggers. And some of the register
> offsets are changed.
>
> The commands to configure CTI triggers are the same as ARM's CTI.
>
> Changes in v5:
> 1. Move common part in qcom-cti.h to coresight-cti.h.
> 2. Convert trigger usage fields to dynamic bitmaps and arrays.
> 3. Fix holes in struct cti_config to save some space.
> 4. Revert the previous changes related to the claim tag in
>    cti_enable/disable_hw.
> Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/
>
> Changes in v4:
> 1. Read the DEVARCH registers to identify Qualcomm CTI.
> 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and
> coresight_cti_reg_store() functions accordingly.
> 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h.
> Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/
>
> Changes in v3:
> 1. Rename is_extended_cti() to of_is_extended_cti().
> 2. Add the missing 'i' when write the CTI trigger registers.
> 3. Convert the multi-line output in sysfs to single line.
> 4. Initialize offset arrays using designated initializer.
> Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/
>
> Changes in V2:
> 1. Add enum for compatible items.
> 2. Move offset arrays to coresight-cti-core
>
> Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> ---
> Yingchao Deng (2):
>       coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays
>       coresight: cti: Add Qualcomm extended CTI support
>
>  drivers/hwtracing/coresight/coresight-cti-core.c   | 144 +++++++++++++---
>  .../hwtracing/coresight/coresight-cti-platform.c   |  16 +-
>  drivers/hwtracing/coresight/coresight-cti-sysfs.c  | 184 +++++++++++++++------
>  drivers/hwtracing/coresight/coresight-cti.h        |  60 ++++++-
>  drivers/hwtracing/coresight/qcom-cti.h             |  29 ++++
>  5 files changed, 346 insertions(+), 87 deletions(-)
> ---
> base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229
> change-id: 20251016-extended_cti-2a426c8894b1
>
> Best regards,
> --
> Yingchao Deng <yingchao.deng@oss.qualcomm.com>
>


-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

>Hi,
>
>This set is looking good now and appears to be getting close to being ready.
>
>There are a few minor issues in the second patch and a few items that
>need to be confirmed.
>1) I note that you removed the code to prevent calling claim/disclaim.
>Does this mean that you confirm that you have tested the patch update
>for claim tags I posted works on your system?

I just tested this patch, the default value of qcom_cti's CLAIMSET register is 0xf,
and unlike the standard CTI (write 0 is no effect), it can be written with 0. 
So, is it acceptable to write 0 to the claimset register of qcom_cti after reading the
devarch register during the probe phase?

	devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH);
	if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) {
		drvdata->subtype = QCOM_CTI;
		drvdata->offsets = cti_extended_offset;
		writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET);
	} else {
		drvdata->subtype = ARM_STD_CTI;
		drvdata->offsets = cti_normal_offset;
	}

>2) In patch 2 I made some comments in regard to ARCH values - please
>confirm that these are accurate and have been tested as working on
>your system

Yes, the bits 31:20 in qcom_cti's DEVARCH register are 0x8EF.

>3) As mentioned in the comments to patch 2 - you need to update the
>docs for the new sysfs selection file you have added

Will update in v6.

Thanks
Yingchao

>
>Thanks and Regards
>
>Mike
>
>On Mon, 20 Oct 2025 at 08:12, Yingchao Deng
><yingchao.deng@oss.qualcomm.com> wrote:
>>
>> The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI.
>> It allows a debugger to send to trigger events to a processor or to send
>> a trigger event to one or more processors when a trigger event occurs on
>> another processor on the same SoC, or even between SoCs.
>>
>> QCOM extended CTI supports up to 128 triggers. And some of the register
>> offsets are changed.
>>
>> The commands to configure CTI triggers are the same as ARM's CTI.
>>
>> Changes in v5:
>> 1. Move common part in qcom-cti.h to coresight-cti.h.
>> 2. Convert trigger usage fields to dynamic bitmaps and arrays.
>> 3. Fix holes in struct cti_config to save some space.
>> 4. Revert the previous changes related to the claim tag in
>>    cti_enable/disable_hw.
>> Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/
>>
>> Changes in v4:
>> 1. Read the DEVARCH registers to identify Qualcomm CTI.
>> 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and
>> coresight_cti_reg_store() functions accordingly.
>> 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h.
>> Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/
>>
>> Changes in v3:
>> 1. Rename is_extended_cti() to of_is_extended_cti().
>> 2. Add the missing 'i' when write the CTI trigger registers.
>> 3. Convert the multi-line output in sysfs to single line.
>> 4. Initialize offset arrays using designated initializer.
>> Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/
>>
>> Changes in V2:
>> 1. Add enum for compatible items.
>> 2. Move offset arrays to coresight-cti-core
>>
>> Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
>> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
>> ---
>> Yingchao Deng (2):
>>       coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays
>>       coresight: cti: Add Qualcomm extended CTI support
>>
>>  drivers/hwtracing/coresight/coresight-cti-core.c   | 144 +++++++++++++---
>>  .../hwtracing/coresight/coresight-cti-platform.c   |  16 +-
>>  drivers/hwtracing/coresight/coresight-cti-sysfs.c  | 184 +++++++++++++++------
>>  drivers/hwtracing/coresight/coresight-cti.h        |  60 ++++++-
>>  drivers/hwtracing/coresight/qcom-cti.h             |  29 ++++
>>  5 files changed, 346 insertions(+), 87 deletions(-)
>> ---
>> base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229
>> change-id: 20251016-extended_cti-2a426c8894b1
>>
>> Best regards,
>> --
>> Yingchao Deng <yingchao.deng@oss.qualcomm.com>
>>

Hi,

On Mon, 3 Nov 2025 at 08:46, Yingchao Deng
<yingchao.deng@oss.qualcomm.com> wrote:
>
> >Hi,
> >
> >This set is looking good now and appears to be getting close to being ready.
> >
> >There are a few minor issues in the second patch and a few items that
> >need to be confirmed.
> >1) I note that you removed the code to prevent calling claim/disclaim.
> >Does this mean that you confirm that you have tested the patch update
> >for claim tags I posted works on your system?
>
> I just tested this patch, the default value of qcom_cti's CLAIMSET register is 0xf,
> and unlike the standard CTI (write 0 is no effect), it can be written with 0.
> So, is it acceptable to write 0 to the claimset register of qcom_cti after reading the
> devarch register during the probe phase?
>
>         devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH);
>         if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) {
>                 drvdata->subtype = QCOM_CTI;
>                 drvdata->offsets = cti_extended_offset;
>                 writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET);
>         } else {
>                 drvdata->subtype = ARM_STD_CTI;
>                 drvdata->offsets = cti_normal_offset;
>         }
>

OK - if you look at v2 of the cliam tag set you will see we introduce
a "claim_tag_info" attribute to the coresight_device structure. This
is initially set to CS_CLAIM_TAG_UNKNOWN, and on the first
claim/disclaim API call the claim tags validity will be tested and a
value of  CS_CLAIM_TAG_STD_PROTOCOL or  CS_CLAIM_TAG_NOT_IMPL set,
skipping the test on all subsequent claim calls.

if you set this  in the probe function i.e.  csdev->claim_tag_info =
CS_CLAIM_TAG_NOT_IMPL, then the claim tags will not be used.


whichever method you use, please ensure a comment appears in the code
describing why the workaround is necessary.

Regards

Mike


> >2) In patch 2 I made some comments in regard to ARCH values - please
> >confirm that these are accurate and have been tested as working on
> >your system
>
> Yes, the bits 31:20 in qcom_cti's DEVARCH register are 0x8EF.
>
> >3) As mentioned in the comments to patch 2 - you need to update the
> >docs for the new sysfs selection file you have added
>
> Will update in v6.
>
> Thanks
> Yingchao
>
> >
> >Thanks and Regards
> >
> >Mike
> >
> >On Mon, 20 Oct 2025 at 08:12, Yingchao Deng
> ><yingchao.deng@oss.qualcomm.com> wrote:
> >>
> >> The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI.
> >> It allows a debugger to send to trigger events to a processor or to send
> >> a trigger event to one or more processors when a trigger event occurs on
> >> another processor on the same SoC, or even between SoCs.
> >>
> >> QCOM extended CTI supports up to 128 triggers. And some of the register
> >> offsets are changed.
> >>
> >> The commands to configure CTI triggers are the same as ARM's CTI.
> >>
> >> Changes in v5:
> >> 1. Move common part in qcom-cti.h to coresight-cti.h.
> >> 2. Convert trigger usage fields to dynamic bitmaps and arrays.
> >> 3. Fix holes in struct cti_config to save some space.
> >> 4. Revert the previous changes related to the claim tag in
> >>    cti_enable/disable_hw.
> >> Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/
> >>
> >> Changes in v4:
> >> 1. Read the DEVARCH registers to identify Qualcomm CTI.
> >> 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and
> >> coresight_cti_reg_store() functions accordingly.
> >> 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h.
> >> Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/
> >>
> >> Changes in v3:
> >> 1. Rename is_extended_cti() to of_is_extended_cti().
> >> 2. Add the missing 'i' when write the CTI trigger registers.
> >> 3. Convert the multi-line output in sysfs to single line.
> >> 4. Initialize offset arrays using designated initializer.
> >> Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/
> >>
> >> Changes in V2:
> >> 1. Add enum for compatible items.
> >> 2. Move offset arrays to coresight-cti-core
> >>
> >> Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> >> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> >> ---
> >> Yingchao Deng (2):
> >>       coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays
> >>       coresight: cti: Add Qualcomm extended CTI support
> >>
> >>  drivers/hwtracing/coresight/coresight-cti-core.c   | 144 +++++++++++++---
> >>  .../hwtracing/coresight/coresight-cti-platform.c   |  16 +-
> >>  drivers/hwtracing/coresight/coresight-cti-sysfs.c  | 184 +++++++++++++++------
> >>  drivers/hwtracing/coresight/coresight-cti.h        |  60 ++++++-
> >>  drivers/hwtracing/coresight/qcom-cti.h             |  29 ++++
> >>  5 files changed, 346 insertions(+), 87 deletions(-)
> >> ---
> >> base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229
> >> change-id: 20251016-extended_cti-2a426c8894b1
> >>
> >> Best regards,
> >> --
> >> Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> >>



--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK