Document the device tree bindings for the USB PHY interfaces integrated
with the DWC3 controller on Google Tensor SoCs, starting with G5
generation. The USB PHY on Tensor G5 includes two integrated Synopsys
PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP.
Due to a complete architectural overhaul in the Google Tensor G5, the
existing Samsung/Exynos USB PHY binding for older generations of Google
silicons such as gs101 are no longer compatible, necessitating this new
device tree binding.
Signed-off-by: Roy Luo <royluo@google.com>
---
.../bindings/phy/google,gs5-usb-phy.yaml | 104 ++++++++++++++++++
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml
new file mode 100644
index 000000000000..c92c20eba1ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025, Google LLC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/google,gs5-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor Series (G5+) USB PHY
+
+maintainers:
+ - Roy Luo <royluo@google.com>
+
+description: |
+ Describes the USB PHY interfaces integrated with the DWC3 USB controller on
+ Google Tensor SoCs, starting with the G5 generation.
+ Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP
+ and USB 3.2/DisplayPort combo PHY IP.
+ The hardware can support three PHY interfaces, which are selected using the
+ first phandle argument in the PHY specifier::
+ 0 - USB high-speed.
+ 1 - USB super-speed.
+ 2 - DisplayPort
+
+properties:
+ compatible:
+ const: google,gs5-usb-phy
+
+ reg:
+ items:
+ - description: USB2 PHY configuration registers.
+ - description: USB 3.2/DisplayPort combo PHY top-level registers.
+
+ reg-names:
+ items:
+ - const: u2phy_cfg
+ - const: dp_top
+
+ "#phy-cells":
+ const: 1
+
+ clocks:
+ items:
+ - description: USB2 PHY clock.
+ - description: USB2 PHY APB clock.
+
+ clock-names:
+ items:
+ - const: usb2_phy
+ - const: u2phy_apb
+
+ resets:
+ items:
+ - description: USB2 PHY reset.
+ - description: USB2 PHY APB reset.
+
+ reset-names:
+ items:
+ - const: usb2_phy
+ - const: u2phy_apb
+
+ power-domains:
+ maxItems: 1
+
+ orientation-switch:
+ type: boolean
+ description:
+ Indicates the PHY as a handler of USB Type-C orientation changes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - orientation-switch
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb_phy: usb_phy@c450014 {
+ compatible = "google,gs5-usb-phy";
+ reg = <0 0x0c450014 0 0xc>,
+ <0 0x0c637000 0 0xa0>;
+ reg-names = "u2phy_cfg", "dp_top";
+ #phy-cells = <1>;
+ clocks = <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>;
+ clock-names = "usb2_phy", "u2phy_apb";
+ resets = <&hsion_resets_usb2_phy>,
+ <&hsion_resets_u2phy_apb>;
+ reset-names = "usb2_phy", "u2phy_apb";
+ power-domains = <&hsio_n_usb_pd>;
+ orientation-switch;
+ };
+ };
+...
--
2.51.0.858.gf9c4a03a3a-googOn Fri, Oct 17, 2025 at 11:51:58PM +0000, Roy Luo wrote: > Document the device tree bindings for the USB PHY interfaces integrated > with the DWC3 controller on Google Tensor SoCs, starting with G5 > generation. The USB PHY on Tensor G5 includes two integrated Synopsys > PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. > > Due to a complete architectural overhaul in the Google Tensor G5, the > existing Samsung/Exynos USB PHY binding for older generations of Google > silicons such as gs101 are no longer compatible, necessitating this new > device tree binding. > > Signed-off-by: Roy Luo <royluo@google.com> > --- > .../bindings/phy/google,gs5-usb-phy.yaml | 104 ++++++++++++++++++ > 1 file changed, 104 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml > new file mode 100644 > index 000000000000..c92c20eba1ea > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml > @@ -0,0 +1,104 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2025, Google LLC > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/google,gs5-usb-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Google Tensor Series (G5+) USB PHY > + > +maintainers: > + - Roy Luo <royluo@google.com> > + > +description: | > + Describes the USB PHY interfaces integrated with the DWC3 USB controller on > + Google Tensor SoCs, starting with the G5 generation. > + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP > + and USB 3.2/DisplayPort combo PHY IP. > + The hardware can support three PHY interfaces, which are selected using the > + first phandle argument in the PHY specifier:: Just one ':', anyway this sentence and below does not belong to description but to phy-cells. You describe the cells. Or just mention the header with IDs - here or in phy-cells. > + 0 - USB high-speed. > + 1 - USB super-speed. > + 2 - DisplayPort > + > +properties: > + compatible: > + const: google,gs5-usb-phy > + > + reg: > + items: > + - description: USB2 PHY configuration registers. > + - description: USB 3.2/DisplayPort combo PHY top-level registers. > + > + reg-names: > + items: > + - const: u2phy_cfg > + - const: dp_top > + > + "#phy-cells": > + const: 1 > + > + clocks: > + items: > + - description: USB2 PHY clock. > + - description: USB2 PHY APB clock. > + > + clock-names: > + items: > + - const: usb2_phy core > + - const: u2phy_apb apb > + > + resets: > + items: > + - description: USB2 PHY reset. > + - description: USB2 PHY APB reset. > + > + reset-names: > + items: > + - const: usb2_phy > + - const: u2phy_apb Same here > + > + power-domains: > + maxItems: 1 Best regards, Krzysztof
On Wed, Oct 22, 2025 at 11:43 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Fri, Oct 17, 2025 at 11:51:58PM +0000, Roy Luo wrote: > > Document the device tree bindings for the USB PHY interfaces integrated > > with the DWC3 controller on Google Tensor SoCs, starting with G5 > > generation. The USB PHY on Tensor G5 includes two integrated Synopsys > > PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. > > > > Due to a complete architectural overhaul in the Google Tensor G5, the > > existing Samsung/Exynos USB PHY binding for older generations of Google > > silicons such as gs101 are no longer compatible, necessitating this new > > device tree binding. > > > > Signed-off-by: Roy Luo <royluo@google.com> > > --- > > .../bindings/phy/google,gs5-usb-phy.yaml | 104 ++++++++++++++++++ > > 1 file changed, 104 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml > > new file mode 100644 > > index 000000000000..c92c20eba1ea > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml > > @@ -0,0 +1,104 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (C) 2025, Google LLC > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/google,gs5-usb-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Google Tensor Series (G5+) USB PHY > > + > > +maintainers: > > + - Roy Luo <royluo@google.com> > > + > > +description: | > > + Describes the USB PHY interfaces integrated with the DWC3 USB controller on > > + Google Tensor SoCs, starting with the G5 generation. > > + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP > > + and USB 3.2/DisplayPort combo PHY IP. > > + The hardware can support three PHY interfaces, which are selected using the > > + first phandle argument in the PHY specifier:: > > Just one ':', anyway this sentence and below does not belong to > description but to phy-cells. You describe the cells. > > Or just mention the header with IDs - here or in phy-cells. > > > + 0 - USB high-speed. > > + 1 - USB super-speed. > > + 2 - DisplayPort > > + > > +properties: > > + compatible: > > + const: google,gs5-usb-phy > > + > > + reg: > > + items: > > + - description: USB2 PHY configuration registers. > > + - description: USB 3.2/DisplayPort combo PHY top-level registers. > > + > > + reg-names: > > + items: > > + - const: u2phy_cfg > > + - const: dp_top > > + > > + "#phy-cells": > > + const: 1 > > + > > + clocks: > > + items: > > + - description: USB2 PHY clock. > > + - description: USB2 PHY APB clock. > > + > > + clock-names: > > + items: > > + - const: usb2_phy > > core > > > + - const: u2phy_apb > > apb > Just to provide the full context, these two clocks/resets (usb2_phy and u2phy_apb) are specifically for eUSB2 PHY. USB3/DP combo PHY has its own clock/reset that hasn't been added yet, we would have to differentiate them once USB3 support is added in the future. I'm fine with the suggested name change, and we can address the naming again when USB3 is ready for integration. Regards, Roy Luo > > + > > + resets: > > + items: > > + - description: USB2 PHY reset. > > + - description: USB2 PHY APB reset. > > + > > + reset-names: > > + items: > > + - const: usb2_phy > > + - const: u2phy_apb > > Same here > > > + > > + power-domains: > > + maxItems: 1 > > Best regards, > Krzysztof >
On 24/10/2025 00:22, Roy Luo wrote: >>> + >>> + clocks: >>> + items: >>> + - description: USB2 PHY clock. >>> + - description: USB2 PHY APB clock. >>> + >>> + clock-names: >>> + items: >>> + - const: usb2_phy >> >> core >> >>> + - const: u2phy_apb >> >> apb >> > > Just to provide the full context, these two clocks/resets > (usb2_phy and u2phy_apb) are specifically for eUSB2 PHY. > USB3/DP combo PHY has its own clock/reset that hasn't > been added yet, we would have to differentiate them once That's confusing a bit. You must add all clocks, all resets, all power domains, all pins etc. Bindings are supposed to be complete, see writing bindings doc. Best regards, Krzysztof
On Mon, Oct 27, 2025 at 7:02 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 24/10/2025 00:22, Roy Luo wrote: > >>> + > >>> + clocks: > >>> + items: > >>> + - description: USB2 PHY clock. > >>> + - description: USB2 PHY APB clock. > >>> + > >>> + clock-names: > >>> + items: > >>> + - const: usb2_phy > >> > >> core > >> > >>> + - const: u2phy_apb > >> > >> apb > >> > > > > Just to provide the full context, these two clocks/resets > > (usb2_phy and u2phy_apb) are specifically for eUSB2 PHY. > > USB3/DP combo PHY has its own clock/reset that hasn't > > been added yet, we would have to differentiate them once > > That's confusing a bit. You must add all clocks, all resets, all power > domains, all pins etc. Bindings are supposed to be complete, see writing > bindings doc. > > > Best regards, > Krzysztof Ok found this in the writing binding doc: "DO attempt to make bindings complete even if a driver doesn’t support some features. For example, if a device has an interrupt, then include the ‘interrupts’ property even if the driver is only polled mode." I will add all the clocks and resets inclusive of usb3 in the next version. Thanks, Roy Luo
On 23/10/2025 08:43, Krzysztof Kozlowski wrote: > On Fri, Oct 17, 2025 at 11:51:58PM +0000, Roy Luo wrote: >> Document the device tree bindings for the USB PHY interfaces integrated >> with the DWC3 controller on Google Tensor SoCs, starting with G5 >> generation. The USB PHY on Tensor G5 includes two integrated Synopsys >> PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. >> >> Due to a complete architectural overhaul in the Google Tensor G5, the >> existing Samsung/Exynos USB PHY binding for older generations of Google >> silicons such as gs101 are no longer compatible, necessitating this new >> device tree binding. >> >> Signed-off-by: Roy Luo <royluo@google.com> >> --- >> .../bindings/phy/google,gs5-usb-phy.yaml | 104 ++++++++++++++++++ >> 1 file changed, 104 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml >> new file mode 100644 >> index 000000000000..c92c20eba1ea >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml >> @@ -0,0 +1,104 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (C) 2025, Google LLC >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/google,gs5-usb-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Google Tensor Series (G5+) USB PHY >> + >> +maintainers: >> + - Roy Luo <royluo@google.com> >> + >> +description: | >> + Describes the USB PHY interfaces integrated with the DWC3 USB controller on >> + Google Tensor SoCs, starting with the G5 generation. >> + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP >> + and USB 3.2/DisplayPort combo PHY IP. >> + The hardware can support three PHY interfaces, which are selected using the >> + first phandle argument in the PHY specifier:: > > Just one ':', anyway this sentence and below does not belong to > description but to phy-cells. You describe the cells. > > Or just mention the header with IDs - here or in phy-cells. If you go with free-form text description in phy cells, then some example could be: renesas,rcar-gen2-usb-phy.yaml For the header (in this case clocks): display/msm/dsi-phy-common.yaml Best regards, Krzysztof
On Wed, Oct 22, 2025 at 11:58 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 23/10/2025 08:43, Krzysztof Kozlowski wrote: > > On Fri, Oct 17, 2025 at 11:51:58PM +0000, Roy Luo wrote: > >> Document the device tree bindings for the USB PHY interfaces integrated > >> with the DWC3 controller on Google Tensor SoCs, starting with G5 > >> generation. The USB PHY on Tensor G5 includes two integrated Synopsys > >> PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. > >> > >> Due to a complete architectural overhaul in the Google Tensor G5, the > >> existing Samsung/Exynos USB PHY binding for older generations of Google > >> silicons such as gs101 are no longer compatible, necessitating this new > >> device tree binding. > >> > >> Signed-off-by: Roy Luo <royluo@google.com> > >> --- > >> .../bindings/phy/google,gs5-usb-phy.yaml | 104 ++++++++++++++++++ > >> 1 file changed, 104 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml > >> new file mode 100644 > >> index 000000000000..c92c20eba1ea > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml > >> @@ -0,0 +1,104 @@ > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >> +# Copyright (C) 2025, Google LLC > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/phy/google,gs5-usb-phy.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: Google Tensor Series (G5+) USB PHY > >> + > >> +maintainers: > >> + - Roy Luo <royluo@google.com> > >> + > >> +description: | > >> + Describes the USB PHY interfaces integrated with the DWC3 USB controller on > >> + Google Tensor SoCs, starting with the G5 generation. > >> + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP > >> + and USB 3.2/DisplayPort combo PHY IP. > >> + The hardware can support three PHY interfaces, which are selected using the > >> + first phandle argument in the PHY specifier:: > > > > Just one ':', anyway this sentence and below does not belong to > > description but to phy-cells. You describe the cells. > > > > Or just mention the header with IDs - here or in phy-cells. > > > If you go with free-form text description in phy cells, then some > example could be: > renesas,rcar-gen2-usb-phy.yaml > > For the header (in this case clocks): > display/msm/dsi-phy-common.yaml > > > Best regards, > Krzysztof Krzysztof, Thanks a lot for providing the reference! I will go with the free-form text description in phy cells following renesas,rcar-gen2-usb-phy.yaml in the next version. Thanks, Roy Luo
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