From: Jie Zhang <quic_jiezh@quicinc.com>
Add gpu and rgmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm6150.dtsi | 112 +++++++++++++++++++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
index e62b062c543657b6fd8f9aba7ad595855d8134d6..8181f63e4d6838b1d198972199756271707e6e49 100644
--- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
@@ -508,6 +508,11 @@ rproc_adsp_mem: rproc-adsp@95900000 {
reg = <0x0 0x95900000 0x0 0x1e00000>;
no-map;
};
+
+ pil_gpu_mem: pil-gpu@97715000 {
+ reg = <0x0 0x97715000 0x0 0x2000>;
+ no-map;
+ };
};
soc: soc@0 {
@@ -1687,6 +1692,113 @@ data-pins {
};
};
+ gpu: gpu@5000000 {
+ compatible = "qcom,adreno-612.0", "qcom,adreno";
+ reg = <0x0 0x05000000 0x0 0x90000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>;
+ clock-names = "core";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ iommus = <&adreno_smmu 0x0 0x401>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ qcom,gmu = <&rgmu>;
+
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&pil_gpu_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ opp-peak-kBps = <7050000>;
+ };
+
+ opp-745000000 {
+ opp-hz = /bits/ 64 <745000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ opp-peak-kBps = <6075000>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5287500>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <3975000>;
+ };
+
+ opp-435000000 {
+ opp-hz = /bits/ 64 <435000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <3000000>;
+ };
+
+ opp-290000000 {
+ opp-hz = /bits/ 64 <290000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1762500>;
+ };
+ };
+ };
+
+ rgmu: rgmu@506a000 {
+ compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
+ reg = <0x0 0x0506a000 0x0 0x34000>;
+ reg-names = "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "smmu_vote";
+
+ power-domains = <&gpucc CX_GDSC>,
+ <&gpucc GX_GDSC>,
+ <&rpmhpd RPMHPD_CX>;
+ power-domain-names = "cx", "gx", "vdd_cx";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "oob", "gmu";
+
+ operating-points-v2 = <&rgmu_opp_table>;
+
+ rgmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+ };
+ };
+
gpucc: clock-controller@5090000 {
compatible = "qcom,qcs615-gpucc";
reg = <0 0x05090000 0 0x9000>;
--
2.51.0On 10/17/25 7:08 PM, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Add gpu and rgmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
[...]
> + gpu_zap_shader: zap-shader {
> + memory-region = <&pil_gpu_mem>;
> + };
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-845000000 {
> + opp-hz = /bits/ 64 <845000000>;
> + required-opps = <&rpmhpd_opp_turbo>;
> + opp-peak-kBps = <7050000>;
Are there speed bins?
[...]
> + rgmu: rgmu@506a000 {
> + compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
> + reg = <0x0 0x0506a000 0x0 0x34000>;
> + reg-names = "gmu";
> +
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> + clock-names = "gmu",
> + "cxo",
> + "axi",
> + "memnoc",
> + "smmu_vote";
> +
> + power-domains = <&gpucc CX_GDSC>,
> + <&gpucc GX_GDSC>,
> + <&rpmhpd RPMHPD_CX>;
> + power-domain-names = "cx", "gx", "vdd_cx";
I think the gpucc node should reference _CX directly instead,
then genpd/opp should trickle the requirements up the chain
> +
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "oob", "gmu";
1 a line, please
lgtm otherwise
Konrad
On 10/22/2025 8:57 PM, Konrad Dybcio wrote:
> On 10/17/25 7:08 PM, Akhil P Oommen wrote:
>> From: Jie Zhang <quic_jiezh@quicinc.com>
>>
>> Add gpu and rgmu nodes for qcs615 chipset.
>>
>> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>
> [...]
>
>> + gpu_zap_shader: zap-shader {
>> + memory-region = <&pil_gpu_mem>;
>> + };
>> +
>> + gpu_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-845000000 {
>> + opp-hz = /bits/ 64 <845000000>;
>> + required-opps = <&rpmhpd_opp_turbo>;
>> + opp-peak-kBps = <7050000>;
>
> Are there speed bins?
None I am aware of as of now.
>
> [...]
>
>> + rgmu: rgmu@506a000 {
>> + compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
>> + reg = <0x0 0x0506a000 0x0 0x34000>;
>> + reg-names = "gmu";
>> +
>> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
>> + <&gpucc GPU_CC_CXO_CLK>,
>> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
>> + clock-names = "gmu",
>> + "cxo",
>> + "axi",
>> + "memnoc",
>> + "smmu_vote";
>> +
>> + power-domains = <&gpucc CX_GDSC>,
>> + <&gpucc GX_GDSC>,
>> + <&rpmhpd RPMHPD_CX>;
>> + power-domain-names = "cx", "gx", "vdd_cx";
>
> I think the gpucc node should reference _CX directly instead,
> then genpd/opp should trickle the requirements up the chain
Do you mean the CX rail scaling here should be handled by gpucc clk driver?
>
>> +
>> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "oob", "gmu";
>
> 1 a line, please
Ack. Thanks
-Akhil
>
> lgtm otherwise
>
> Konrad
On 10/24/25 12:17 AM, Akhil P Oommen wrote:
> On 10/22/2025 8:57 PM, Konrad Dybcio wrote:
>> On 10/17/25 7:08 PM, Akhil P Oommen wrote:
>>> From: Jie Zhang <quic_jiezh@quicinc.com>
>>>
>>> Add gpu and rgmu nodes for qcs615 chipset.
>>>
>>> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
>>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>>> ---
[...]
>>> + rgmu: rgmu@506a000 {
>>> + compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
>>> + reg = <0x0 0x0506a000 0x0 0x34000>;
>>> + reg-names = "gmu";
>>> +
>>> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
>>> + <&gpucc GPU_CC_CXO_CLK>,
>>> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>>> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
>>> + clock-names = "gmu",
>>> + "cxo",
>>> + "axi",
>>> + "memnoc",
>>> + "smmu_vote";
>>> +
>>> + power-domains = <&gpucc CX_GDSC>,
>>> + <&gpucc GX_GDSC>,
>>> + <&rpmhpd RPMHPD_CX>;
>>> + power-domain-names = "cx", "gx", "vdd_cx";
>>
>> I think the gpucc node should reference _CX directly instead,
>> then genpd/opp should trickle the requirements up the chain
>
> Do you mean the CX rail scaling here should be handled by gpucc clk driver?
Yes, you can simply add .use_rpm = true to qcom_cc_desc in there and
add power-domains = <&rpmhpd RPMHPD_CX> to the node
Konrad
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