Glymur is the next generation compute SoC of Qualcomm. This patch series
aims to add support for the fourth, fifth and sixth PCIe instance on it.
The fifth PCIe instance on Glymur has a Gen5 4-lane PHY and fourth, fifth
and sixth PCIe instance have a Gen5 2-lane PHY.
The device tree changes and whatever driver patches that are not part of
this patch series will be posted separately after official announcement of
the SOC.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Changes in v5:
- Rebase patches on 6.18-rc1.
- Add PCIe Gen4 x2 support.
- Link to v4: https://lore.kernel.org/all/20250903-glymur_pcie5-v4-0-c187c2d9d3bd@oss.qualcomm.com/
Changes in v4:
- Rebase Patch[1/4] onto next branch of linux-phy.
- Rebase Patch[4/4] onto next branch of linux-phy.
- Link to v3: https://lore.kernel.org/r/20250825-glymur_pcie5-v3-0-5c1d1730c16f@oss.qualcomm.com
Changes in v3:
- Keep qmp_pcie_of_match_table array sorted.
- Drop qref supply for PCIe Gen5x4 PHY.
- Link to v2: https://lore.kernel.org/r/20250821-glymur_pcie5-v2-0-cd516784ef20@oss.qualcomm.com
Changes in v2:
- Add offsets of PLL and TXRXZ register blocks for v8.50 PHY in Patch[4/4].
- Link to v1: https://lore.kernel.org/r/20250819-glymur_pcie5-v1-0-2ea09f83cbb0@oss.qualcomm.com
---
Prudhvi Yarlagadda (4):
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY
dt-bindings: PCI: qcom: Document the Glymur PCIe Controller
phy: qcom-qmp: pcs: Add v8.50 register offsets
phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY
Qiang Yu (2):
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe Gen4 2-lane PHY
phy: qcom: qmp-pcie: Add support for glymur PCIe Gen4 x2 PHY
.../bindings/pci/qcom,pcie-x1e80100.yaml | 7 ++-
.../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 +++
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 60 ++++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8_50.h | 13 +++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 2 +
5 files changed, 87 insertions(+), 1 deletion(-)
---
base-commit: 98ac9cc4b4452ed7e714eddc8c90ac4ae5da1a09
change-id: 20251017-glymur_pcie-88b45bf2e498
Best regards,
--
Qiang Yu <qiang.yu@oss.qualcomm.com>