[v1] arm64: dts: mediatek: Add Openwrt One AP functionality

[PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

Posted by Sjoerd Simons 3 months, 3 weeks ago

Enable the Ethernet subsystem on OpenWrt One board with dual-MAC
configuration:
- GMAC0: Connected to external Airoha EN8811H 2.5GbE PHY via SGMII
  (2500base-x mode) for WAN connectivity with LED indicators
- GMAC1: Connected to internal MT7981 1GbE PHY (GMII mode) for LAN

Ethernet aliases are defined to provide consistent network interface
naming (ethernet0 = LAN, ethernet1 = WAN).

Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
---
 .../boot/dts/mediatek/mt7981b-openwrt-one.dts      | 58 ++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
index 9878009385cc6..6e6e4f1515f67 100644
--- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
@@ -3,6 +3,8 @@
 /dts-v1/;
 
 #include "mt7981b.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 #include "dt-bindings/pinctrl/mt65xx.h"
 
 / {
@@ -10,6 +12,8 @@ / {
 	model = "OpenWrt One";
 
 	aliases {
+		ethernet0 = &gmac1;
+		ethernet1 = &gmac0;
 		serial0 = &uart0;
 	};
 
@@ -41,6 +45,56 @@ reg_5v: regulator-5v {
 	};
 };
 
+&eth {
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		nvmem-cells = <&macaddr_factory_24 0>;
+		nvmem-cell-names = "mac-address";
+		phy-mode = "2500base-x";
+		phy-handle = <&phy15>;
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+	};
+};
+
+&mdio_bus {
+	phy15: ethernet-phy@f {
+		compatible = "ethernet-phy-id03a2.a411";
+		reg = <0xf>;
+		interrupt-parent = <&pio>;
+		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
+		reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <20000>;
+		airoha,pnswap-rx;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@0 {
+				reg = <0>;
+				function = LED_FUNCTION_WAN;
+				color = <LED_COLOR_ID_AMBER>;
+			};
+
+			led@1 {
+				reg = <1>;
+				function = LED_FUNCTION_WAN;
+				color = <LED_COLOR_ID_GREEN>;
+			};
+		};
+	};
+};
+
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_pins>;
@@ -145,6 +199,10 @@ partition@180000 {
 	};
 };
 
+&sgmiisys0 {
+	mediatek,pnswap;
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins>;

-- 
2.51.0

Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

Posted by Andrew Lunn 3 months, 3 weeks ago

> +&mdio_bus {
> +	phy15: ethernet-phy@f {
> +		compatible = "ethernet-phy-id03a2.a411";
> +		reg = <0xf>;
> +		interrupt-parent = <&pio>;
> +		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;

This is probably wrong. PHY interrupts are generally level, not edge.

	Andrew

Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

Posted by Sjoerd Simons 3 months, 2 weeks ago

On Fri, 2025-10-17 at 19:31 +0200, Andrew Lunn wrote:
> > +&mdio_bus {
> > +	phy15: ethernet-phy@f {
> > +		compatible = "ethernet-phy-id03a2.a411";
> > +		reg = <0xf>;
> > +		interrupt-parent = <&pio>;
> > +		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
> 
> This is probably wrong. PHY interrupts are generally level, not edge.

Sadly i can't find a datasheet for the PHY, so can't really validate that easily. Maybe Eric can
comment here as the author of the relevant PHY driver.

I'd note that the mt7986a-bananapi-bpi-r3-mini dts has the same setup for this PHY, however that's
ofcourse not authoritative.

-- 
Sjoerd Simons <sjoerd@collabora.com>

Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

Posted by Eric Woudstra 3 months, 1 week ago


On 10/21/25 10:21 PM, Sjoerd Simons wrote:
> On Fri, 2025-10-17 at 19:31 +0200, Andrew Lunn wrote:
>>> +&mdio_bus {
>>> +	phy15: ethernet-phy@f {
>>> +		compatible = "ethernet-phy-id03a2.a411";
>>> +		reg = <0xf>;
>>> +		interrupt-parent = <&pio>;
>>> +		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
>>
>> This is probably wrong. PHY interrupts are generally level, not edge.
> 
> Sadly i can't find a datasheet for the PHY, so can't really validate that easily. Maybe Eric can
> comment here as the author of the relevant PHY driver.
> 
> I'd note that the mt7986a-bananapi-bpi-r3-mini dts has the same setup for this PHY, however that's
> ofcourse not authoritative.
> 

Lucien would have access to the correct information about the interrupt.

Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

Posted by Sjoerd Simons 3 months, 1 week ago

On Tue, 2025-10-28 at 12:14 +0100, Eric Woudstra wrote:
> 
> 
> On 10/21/25 10:21 PM, Sjoerd Simons wrote:
> > On Fri, 2025-10-17 at 19:31 +0200, Andrew Lunn wrote:
> > > > +&mdio_bus {
> > > > +	phy15: ethernet-phy@f {
> > > > +		compatible = "ethernet-phy-id03a2.a411";
> > > > +		reg = <0xf>;
> > > > +		interrupt-parent = <&pio>;
> > > > +		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
> > > 
> > > This is probably wrong. PHY interrupts are generally level, not edge.
> > 
> > Sadly i can't find a datasheet for the PHY, so can't really validate that
> > easily. Maybe Eric can
> > comment here as the author of the relevant PHY driver.
> > 
> > I'd note that the mt7986a-bananapi-bpi-r3-mini dts has the same setup for
> > this PHY, however that's
> > ofcourse not authoritative.
> > 
> 
> Lucien would have access to the correct information about the interrupt.

Thanks! For what it's worth i got around to putting a scope on the line last
night. It looks like the interrupt line is pulled down until cleared, so it
appears it's indeed a Level interrupt as Andrew guessed. But would be great to
have this confirmed based on the documentation :)

-- 
Sjoerd Simons <sjoerd@collabora.com>
Collabora

Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

Posted by Lucien.Jheng 3 months, 1 week ago

Hi

Sjoerd Simons 於 2025/10/28 下午 09:24 寫道:
> On Tue, 2025-10-28 at 12:14 +0100, Eric Woudstra wrote:
>>
>> On 10/21/25 10:21 PM, Sjoerd Simons wrote:
>>> On Fri, 2025-10-17 at 19:31 +0200, Andrew Lunn wrote:
>>>>> +&mdio_bus {
>>>>> +	phy15: ethernet-phy@f {
>>>>> +		compatible = "ethernet-phy-id03a2.a411";
>>>>> +		reg = <0xf>;
>>>>> +		interrupt-parent = <&pio>;
>>>>> +		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
>>>> This is probably wrong. PHY interrupts are generally level, not edge.
>>> Sadly i can't find a datasheet for the PHY, so can't really validate that
>>> easily. Maybe Eric can
>>> comment here as the author of the relevant PHY driver.
>>>
>>> I'd note that the mt7986a-bananapi-bpi-r3-mini dts has the same setup for
>>> this PHY, however that's
>>> ofcourse not authoritative.
>>>
>> Lucien would have access to the correct information about the interrupt.
> Thanks! For what it's worth i got around to putting a scope on the line last
> night. It looks like the interrupt line is pulled down until cleared, so it
> appears it's indeed a Level interrupt as Andrew guessed. But would be great to
> have this confirmed based on the documentation :)

The Airoha EN8811H Interrupt behavior is as follows:

When the line side link changes (up→ down or down → up), GPIO 8 will 
output low.

After you clear the interrupt, GPIO 8 will go high. Regarding the 
documentation, let me check where I can put it.

If you have any questions about the EN8811H, please feel free to discuss 
with me.

Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

Posted by Andrew Lunn 3 months, 2 weeks ago

On Tue, Oct 21, 2025 at 10:21:31PM +0200, Sjoerd Simons wrote:
> On Fri, 2025-10-17 at 19:31 +0200, Andrew Lunn wrote:
> > > +&mdio_bus {
> > > +	phy15: ethernet-phy@f {
> > > +		compatible = "ethernet-phy-id03a2.a411";
> > > +		reg = <0xf>;
> > > +		interrupt-parent = <&pio>;
> > > +		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
> > 
> > This is probably wrong. PHY interrupts are generally level, not edge.
> 
> Sadly i can't find a datasheet for the PHY, so can't really validate that easily.

What PHY is it? Look at the .handle_interrupt function in the
driver. If the hardware supports a single interrupt bit, it could in
theory support edge. However, as soon as you have multiple bits, you
need level, to avoid races where an interrupt happens while you are
clearing other interrupts.

	 Andrew

Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

Posted by Sjoerd Simons 3 months, 2 weeks ago

On Tue, 2025-10-21 at 22:40 +0200, Andrew Lunn wrote:
> On Tue, Oct 21, 2025 at 10:21:31PM +0200, Sjoerd Simons wrote:
> > On Fri, 2025-10-17 at 19:31 +0200, Andrew Lunn wrote:
> > > > +&mdio_bus {
> > > > +	phy15: ethernet-phy@f {
> > > > +		compatible = "ethernet-phy-id03a2.a411";
> > > > +		reg = <0xf>;
> > > > +		interrupt-parent = <&pio>;
> > > > +		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
> > > 
> > > This is probably wrong. PHY interrupts are generally level, not edge.
> > 
> > Sadly i can't find a datasheet for the PHY, so can't really validate that
> > easily.
> 
> What PHY is it? Look at the .handle_interrupt function in the
> driver. If the hardware supports a single interrupt bit, it could in
> theory support edge. However, as soon as you have multiple bits, you
> need level, to avoid races where an interrupt happens while you are
> clearing other interrupts.

ethernet-phy-id03a2.a411 is Airoha EN8811H (air_en8811h driver). Handle
interrupt there seems to just be a general interrupt clear followed by a
`phy_trigger_machine`. It doesn't seem to read specific interrupt status. 

Testing with IRQ_TYPE_LEVEL_LOW does seem to work as expected and results in
detecting 4 interrupts rather then just 1 with edges when enabling the
interface. However I'm not sure what can be concluded from that if anything :)..

I can stick a scope on the line in the coming days to see how the interrupt line
behaves if interrupts aren't cleared, which may clarify things.

-- 
Sjoerd Simons
Collabora