The ADC available in the r9a06g032 SoC can use up to two internal ACD
cores (ADC1 and ADC2) those internal cores are handled through ADC
controller virtual channels.

Describe this device.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
 arch/arm/boot/dts/renesas/r9a06g032.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 13a60656b044..2bc07372bafa 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -290,6 +290,16 @@ i2c2: i2c@40064000 {
 			status = "disabled";
 		};
 
+		adc: adc@40065000 {
+			compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc";
+			reg = <0x40065000 0x200>;
+			clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>;
+			clock-names = "pclk", "adc-clk";
+			power-domains = <&sysctrl>;
+			#io-channel-cells = <1>;
+			status = "disabled";
+		};
+
 		pinctrl: pinctrl@40067000 {
 			compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
 			reg = <0x40067000 0x1000>, <0x51000000 0x480>;
-- 
2.51.0

On Wed, Oct 15, 2025 at 04:28:15PM +0200, Herve Codina (Schneider Electric) wrote:
> The ADC available in the r9a06g032 SoC can use up to two internal ACD
> cores (ADC1 and ADC2) those internal cores are handled through ADC
> controller virtual channels.
> 
> Describe this device.
> 
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>

Looks good given the current bindings. Despite clock-names will need an update:

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>