From: Konrad Dybcio <konrad.dybcio@linaro.org>

Some IOMMUs on some platforms (there doesn't seem to be a good denominator
for this) require the presence of a third clock, specifically for
accessing the IOMMU's Translation Buffer Unit (TBU). Allow it.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Resending from a 2023 megaseries, no changes

v1: https://lore.kernel.org/lkml/20230627-topic-more_bindings-v1-7-6b4b6cd081e5@linaro.org/
---
 Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
index 3e5623edd207..93a489025317 100644
--- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
@@ -32,14 +32,18 @@ properties:
           - const: qcom,msm-iommu-v2
 
   clocks:
+    minItems: 2
     items:
       - description: Clock required for IOMMU register group access
       - description: Clock required for underlying bus access
+      - description: Clock required for Translation Buffer Unit access
 
   clock-names:
+    minItems: 2
     items:
       - const: iface
       - const: bus
+      - const: tbu
 
   power-domains:
     maxItems: 1

---
base-commit: f5450b214b2440192a238d0c4af9f725810f8e01
change-id: 20251015-topic-qciommu_bindings_fix-3bf3904041b9

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

On 2025-10-15 5:41 pm, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> Some IOMMUs on some platforms (there doesn't seem to be a good denominator
> for this) require the presence of a third clock, specifically for
> accessing the IOMMU's Translation Buffer Unit (TBU). Allow it.

Hmmm, but isn't the only thing that accesses TBUs the consumer of the 
qcom,tbu binding, which already has its own clock?

Thanks,
Robin.

> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> Resending from a 2023 megaseries, no changes
> 
> v1: https://lore.kernel.org/lkml/20230627-topic-more_bindings-v1-7-6b4b6cd081e5@linaro.org/
> ---
>   Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
> index 3e5623edd207..93a489025317 100644
> --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
> @@ -32,14 +32,18 @@ properties:
>             - const: qcom,msm-iommu-v2
>   
>     clocks:
> +    minItems: 2
>       items:
>         - description: Clock required for IOMMU register group access
>         - description: Clock required for underlying bus access
> +      - description: Clock required for Translation Buffer Unit access
>   
>     clock-names:
> +    minItems: 2
>       items:
>         - const: iface
>         - const: bus
> +      - const: tbu
>   
>     power-domains:
>       maxItems: 1
> 
> ---
> base-commit: f5450b214b2440192a238d0c4af9f725810f8e01
> change-id: 20251015-topic-qciommu_bindings_fix-3bf3904041b9
> 
> Best regards,

On Wed, Oct 15, 2025 at 05:48:05PM +0100, Robin Murphy wrote:
> On 2025-10-15 5:41 pm, Konrad Dybcio wrote:
> > From: Konrad Dybcio <konrad.dybcio@linaro.org>
> > 
> > Some IOMMUs on some platforms (there doesn't seem to be a good denominator

It would be nice to provide some examples here.

> > for this) require the presence of a third clock, specifically for
> > accessing the IOMMU's Translation Buffer Unit (TBU). Allow it.
> 
> Hmmm, but isn't the only thing that accesses TBUs the consumer of the
> qcom,tbu binding, which already has its own clock?

qcom,tbu is only defined for normal arm,mmu-500 platforms. Here Konrad
is fixing the older and more obscure Qualcomm virtual MMU device.

> 
> Thanks,
> Robin.
> 
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> > ---
> > Resending from a 2023 megaseries, no changes
> > 
> > v1: https://lore.kernel.org/lkml/20230627-topic-more_bindings-v1-7-6b4b6cd081e5@linaro.org/
> > ---
> >   Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 4 ++++
> >   1 file changed, 4 insertions(+)
> > 
-- 
With best wishes
Dmitry

On 10/15/25 10:10 PM, Dmitry Baryshkov wrote:
> On Wed, Oct 15, 2025 at 05:48:05PM +0100, Robin Murphy wrote:
>> On 2025-10-15 5:41 pm, Konrad Dybcio wrote:
>>> From: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>
>>> Some IOMMUs on some platforms (there doesn't seem to be a good denominator
> 
> It would be nice to provide some examples here.
> 
>>> for this) require the presence of a third clock, specifically for
>>> accessing the IOMMU's Translation Buffer Unit (TBU). Allow it.
>>
>> Hmmm, but isn't the only thing that accesses TBUs the consumer of the
>> qcom,tbu binding, which already has its own clock?
> 
> qcom,tbu is only defined for normal arm,mmu-500 platforms. Here Konrad
> is fixing the older and more obscure Qualcomm virtual MMU device.

(for context: this touches upon 2014-ish platforms)

I checked the address map of the physical MMU500 that lies underneath
this virtual impl and it doesn't fully expose the same registers that
the modern ones do, I only see PWR_STATUS.

The BSP kernels for those oldies don't seem to have a notion of a TBU
either, except for toggling clocks that contain "_TBU" in their name
at both the IOMMU device and some DMA-capable multimedia blocks, which
I suppose makes some sense..

Konrad

On Thu, Oct 16, 2025 at 10:09:58AM +0200, Konrad Dybcio wrote:
> On 10/15/25 10:10 PM, Dmitry Baryshkov wrote:
> > On Wed, Oct 15, 2025 at 05:48:05PM +0100, Robin Murphy wrote:
> >> On 2025-10-15 5:41 pm, Konrad Dybcio wrote:
> >>> From: Konrad Dybcio <konrad.dybcio@linaro.org>
> >>>
> >>> Some IOMMUs on some platforms (there doesn't seem to be a good denominator
> > 
> > It would be nice to provide some examples here.
> > 
> >>> for this) require the presence of a third clock, specifically for
> >>> accessing the IOMMU's Translation Buffer Unit (TBU). Allow it.
> >>
> >> Hmmm, but isn't the only thing that accesses TBUs the consumer of the
> >> qcom,tbu binding, which already has its own clock?
> > 
> > qcom,tbu is only defined for normal arm,mmu-500 platforms. Here Konrad
> > is fixing the older and more obscure Qualcomm virtual MMU device.
> 
> (for context: this touches upon 2014-ish platforms)
> 
> I checked the address map of the physical MMU500 that lies underneath
> this virtual impl and it doesn't fully expose the same registers that
> the modern ones do, I only see PWR_STATUS.
> 
> The BSP kernels for those oldies don't seem to have a notion of a TBU
> either, except for toggling clocks that contain "_TBU" in their name
> at both the IOMMU device and some DMA-capable multimedia blocks, which
> I suppose makes some sense..
> 

On MSM8939 for the &gpu_iommu, the "tbu" clock isn't listed for
accessing the TBU registers, it's necessary to avoid timeouts during TLB
flushes. See Qualcomm Snapdragon 410E Processor (APQ8016E) Technical
Reference Manual, SMMU chapter, section "8.8.3.1.2 Clock gating":

  Clock gating programming guide

    For APPS TCU/TBU (TBU to TCU interface is asynchronous)
    Software should turn ON clock to APPS TCU
      - During APPS TCU register programming sequence

    For GPU TCU/TBU (TBU to TCU interface is synchronous)
    Software should turn ON clock to GPU TBU
      - During GPU TLB invalidation sequence <=====================
    Software should turn ON clock to GPU TCU
      - During GPU TCU register programming sequence
      - While GPU master clock is Active

Might be worth clarifying this in the commit message. It was also
mentioned in commit 5bc1cf1466f6 ("iommu/qcom: add optional 'tbu' clock
for TLB invalidate") (not sure why that commit didn't adjust the
bindings...).

Thanks,
Stephan