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[PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520

Yao Zi posted 5 patches 2 months ago
[PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520
Posted by Yao Zi 2 months ago 
Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
one for AO subsystem is marked as reserved, since it may be used by AON
firmware.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index e680d1a7c821..15d64eaea89f 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -277,6 +277,12 @@ clint: timer@ffdc000000 {
 					      <&cpu3_intc 3>, <&cpu3_intc 7>;
 		};
 
+		rst_vi: reset-controller@ffe4040100 {
+			compatible = "thead,th1520-reset-vi";
+			reg = <0xff 0xe4040100 0x0 0x8>;
+			#reset-cells = <1>;
+		};
+
 		spi0: spi@ffe700c000 {
 			compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
 			reg = <0xff 0xe700c000 0x0 0x1000>;
@@ -502,6 +508,18 @@ uart2: serial@ffec010000 {
 			status = "disabled";
 		};
 
+		rst_misc: reset-controller@ffec02c000 {
+			compatible = "thead,th1520-reset-misc";
+			reg = <0xff 0xec02c000 0x0 0x18>;
+			#reset-cells = <1>;
+		};
+
+		rst_vp: reset-controller@ffecc30000 {
+			compatible = "thead,th1520-reset-vp";
+			reg = <0xff 0xecc30000 0x0 0x14>;
+			#reset-cells = <1>;
+		};
+
 		clk: clock-controller@ffef010000 {
 			compatible = "thead,th1520-clk-ap";
 			reg = <0xff 0xef010000 0x0 0x1000>;
@@ -509,6 +527,18 @@ clk: clock-controller@ffef010000 {
 			#clock-cells = <1>;
 		};
 
+		rst_ap: reset-controller@ffef014000 {
+			compatible = "thead,th1520-reset-ap";
+			reg = <0xff 0xef014000 0x0 0x1000>;
+			#reset-cells = <1>;
+		};
+
+		rst_dsp: reset-controller@ffef040028 {
+			compatible = "thead,th1520-reset-dsp";
+			reg = <0xff 0xef040028 0x0 0x4>;
+			#reset-cells = <1>;
+		};
+
 		gpu: gpu@ffef400000 {
 			compatible = "thead,th1520-gpu", "img,img-bxm-4-64",
 				     "img,img-rogue";
@@ -681,6 +711,13 @@ aogpio: gpio-controller@0 {
 			};
 		};
 
+		rst_ao: reset-controller@fffff44000 {
+			compatible = "thead,th1520-reset-ao";
+			reg = <0xff 0xfff44000 0x0 0x2000>;
+			#reset-cells = <1>;
+			status = "reserved";
+		};
+
 		padctrl_aosys: pinctrl@fffff4a000 {
 			compatible = "thead,th1520-pinctrl";
 			reg = <0xff 0xfff4a000 0x0 0x2000>;
-- 
2.50.1
Re: [PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520
Posted by Drew Fustini 1 month, 1 week ago 
On Tue, Oct 14, 2025 at 01:10:32PM +0000, Yao Zi wrote:
> Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> one for AO subsystem is marked as reserved, since it may be used by AON
> firmware.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)

I've applied this to thead-dt-for-next.

Thanks,
Drew
Re: [PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520
Posted by Drew Fustini 1 month, 2 weeks ago 
On Tue, Oct 14, 2025 at 01:10:32PM +0000, Yao Zi wrote:
> Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> one for AO subsystem is marked as reserved, since it may be used by AON
> firmware.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)

Reviewed-by: Drew Fustini <fustini@kernel.org>

There is a conflict now in next but I will fix it when applying.

Thanks,
Drew
Re: [PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520
Posted by Drew Fustini 1 month, 2 weeks ago 
On Tue, Oct 14, 2025 at 01:10:32PM +0000, Yao Zi wrote:
> Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> one for AO subsystem is marked as reserved, since it may be used by AON
> firmware.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index e680d1a7c821..15d64eaea89f 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -277,6 +277,12 @@ clint: timer@ffdc000000 {
>  					      <&cpu3_intc 3>, <&cpu3_intc 7>;
>  		};
>  
> +		rst_vi: reset-controller@ffe4040100 {
> +			compatible = "thead,th1520-reset-vi";
> +			reg = <0xff 0xe4040100 0x0 0x8>;

Is this intentional so that the first VI_SUBSYS register, VISYS_SW_RST
at offset 0x100, will have an offset of 0 from the thead,th1520-reset-vi
reg in the driver?

[snip]
> +		rst_dsp: reset-controller@ffef040028 {
> +			compatible = "thead,th1520-reset-dsp";
> +			reg = <0xff 0xef040028 0x0 0x4>;

Similar to rst_vi, is this intentional so that the first register,
DSPSYS_SW_RST at offset 0x28, will have an offset of 0 in the driver?

Thanks,
Drew
Re: [PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520
Posted by Yao Zi 1 month, 2 weeks ago 
On Mon, Oct 27, 2025 at 11:56:15AM +0000, Drew Fustini wrote:
> On Tue, Oct 14, 2025 at 01:10:32PM +0000, Yao Zi wrote:
> > Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> > one for AO subsystem is marked as reserved, since it may be used by AON
> > firmware.
> > 
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> > index e680d1a7c821..15d64eaea89f 100644
> > --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> > @@ -277,6 +277,12 @@ clint: timer@ffdc000000 {
> >  					      <&cpu3_intc 3>, <&cpu3_intc 7>;
> >  		};
> >  
> > +		rst_vi: reset-controller@ffe4040100 {
> > +			compatible = "thead,th1520-reset-vi";
> > +			reg = <0xff 0xe4040100 0x0 0x8>;
> 
> Is this intentional so that the first VI_SUBSYS register, VISYS_SW_RST
> at offset 0x100, will have an offset of 0 from the thead,th1520-reset-vi
> reg in the driver?

Yes, it's intentional for both VI and DSP subsystem. As you could see,
excluding these TEE-only shadows, the first reset-related register in
VI_SUBSYS is at offset 0x100. For DSP subsystem, it's at offset 0x28
(and is the only reset-related register).

I want to keep the first 0x100 bytes in VI_SUBSYS, and first 0x24 bytes
in DSP_SUBSYS free, because they're clock-related registers, and should
be reserved for clock driver introduced in the future.

In TH1520 SoC, only AON and AP subsystems have strictly separated reset
and clock register regions. For all other subsystems like VI, VO, VP,
MISC and DSP, reset and clock registers tightly follow each other, but
they don't interleave.

This series follows the way in which VO clock/reset controllers are
modeled in devicetree, where the subsystem region is split into two
nodes, one for clock and one for reset. This will lead to less regular
address/size values like what you noticed, as the registers do stay very
close.

> [snip]
> > +		rst_dsp: reset-controller@ffef040028 {
> > +			compatible = "thead,th1520-reset-dsp";
> > +			reg = <0xff 0xef040028 0x0 0x4>;
> 
> Similar to rst_vi, is this intentional so that the first register,
> DSPSYS_SW_RST at offset 0x28, will have an offset of 0 in the driver?
> 
> Thanks,
> Drew

Best regards,
Yao Zi

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