Add the Device Tree binding for two PCIe PHYs present on the SpacemiT
K1 SoC. These PHYs are dependent on a separate combo PHY, which
determines at probe time the calibration values used by the PCIe-only
PHYs.
Signed-off-by: Alex Elder <elder@riscstar.com>
---
v2: - Added '>' to the description, and reworded it a bit
- Added clocks and clock-names properties
- Dropped the label and status property from the example
.../bindings/phy/spacemit,k1-pcie-phy.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
new file mode 100644
index 0000000000000..c821f6cafcdae
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe PHY
+
+maintainers:
+ - Alex Elder <elder@riscstar.com>
+
+description: >
+ There are two PHYs on the SpacemiT K1 SoC used for PCIe (only).
+ These PHYs must be configured using calibration values that are
+ determined by a third "combo PHY". The combo PHY determines
+ these calibration values during probe so they can be used for
+ the two PCIe-only PHYs.
+
+ The PHY uses an external oscillator as a reference clock. During
+ normal operation, the PCIe host driver is responsible for ensuring
+ all other clocks needed by a PHY are enabled, and all resets
+ affecting the PHY are deasserted.
+
+properties:
+ compatible:
+ const: spacemit,k1-pcie-phy
+
+ reg:
+ items:
+ - description: PHY control registers
+
+ clocks:
+ items:
+ - description: External oscillator used by the PHY PLL
+
+ clock-names:
+ const: refclk
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@c0c10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0xc0c10000 0x1000>;
+ clocks = <&vctcxo_24m>;
+ clock-names = "refclk";
+ #phy-cells = <0>;
+ };
--
2.48.1