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[PATCH net] net: ti: icssg-prueth: Fix fdb hash size configuration

Meghana Malladi posted 1 patch 2 months, 1 week ago
There is a newer version of this series
drivers/net/ethernet/ti/icssg/icssg_config.c | 7 +++++++
1 file changed, 7 insertions(+)
[PATCH net] net: ti: icssg-prueth: Fix fdb hash size configuration
Posted by Meghana Malladi 2 months, 1 week ago 
The ICSSG driver does the initial FDB configuration which
includes setting the control registers. Other run time
management like learning is managed by the PRU's. The default
FDB hash size used by the firmware is 512 slots which is not
aligned with the driver's configuration. Update the driver
FDB config to fix it.

Fixes: abd5576b9c57f ("net: ti: icssg-prueth: Add support for ICSSG switch firmware")
Signed-off-by: Meghana Malladi <m-malladi@ti.com>
---

Please refer trm [1] 6.4.14.12.17 section
on how the FDB config register gets configured.

[1]: https://www.ti.com/lit/pdf/spruim2

 drivers/net/ethernet/ti/icssg/icssg_config.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/ethernet/ti/icssg/icssg_config.c b/drivers/net/ethernet/ti/icssg/icssg_config.c
index da53eb04b0a4..3f8237c17d09 100644
--- a/drivers/net/ethernet/ti/icssg/icssg_config.c
+++ b/drivers/net/ethernet/ti/icssg/icssg_config.c
@@ -66,6 +66,9 @@
 #define FDB_GEN_CFG1		0x60
 #define SMEM_VLAN_OFFSET	8
 #define SMEM_VLAN_OFFSET_MASK	GENMASK(25, 8)
+#define FDB_HASH_SIZE_MASK	GENMASK(6, 3)
+#define FDB_HASH_SIZE_SHIFT	3
+#define FDB_HASH_SIZE		3
 
 #define FDB_GEN_CFG2		0x64
 #define FDB_VLAN_EN		BIT(6)
@@ -463,6 +466,8 @@ void icssg_init_emac_mode(struct prueth *prueth)
 	/* Set VLAN TABLE address base */
 	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK,
 			   addr <<  SMEM_VLAN_OFFSET);
+	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK,
+			   FDB_HASH_SIZE << FDB_HASH_SIZE_SHIFT);
 	/* Set enable VLAN aware mode, and FDBs for all PRUs */
 	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, (FDB_PRU0_EN | FDB_PRU1_EN | FDB_HOST_EN));
 	prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va +
@@ -484,6 +489,8 @@ void icssg_init_fw_offload_mode(struct prueth *prueth)
 	/* Set VLAN TABLE address base */
 	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK,
 			   addr <<  SMEM_VLAN_OFFSET);
+	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK,
+			   FDB_HASH_SIZE << FDB_HASH_SIZE_SHIFT);
 	/* Set enable VLAN aware mode, and FDBs for all PRUs */
 	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, FDB_EN_ALL);
 	prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va +

base-commit: 68a052239fc4b351e961f698b824f7654a346091
-- 
2.43.0
Re: [PATCH net] net: ti: icssg-prueth: Fix fdb hash size configuration
Posted by Simon Horman 2 months, 1 week ago 
On Mon, Oct 13, 2025 at 02:29:25PM +0530, Meghana Malladi wrote:
> The ICSSG driver does the initial FDB configuration which
> includes setting the control registers. Other run time
> management like learning is managed by the PRU's. The default
> FDB hash size used by the firmware is 512 slots which is not
> aligned with the driver's configuration. Update the driver
> FDB config to fix it.
> 
> Fixes: abd5576b9c57f ("net: ti: icssg-prueth: Add support for ICSSG switch firmware")
> Signed-off-by: Meghana Malladi <m-malladi@ti.com>
> ---
> 
> Please refer trm [1] 6.4.14.12.17 section
> on how the FDB config register gets configured.
> 
> [1]: https://www.ti.com/lit/pdf/spruim2

Thanks for the link!
And thanks to TI for publishing this document.

> 
>  drivers/net/ethernet/ti/icssg/icssg_config.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/net/ethernet/ti/icssg/icssg_config.c b/drivers/net/ethernet/ti/icssg/icssg_config.c
> index da53eb04b0a4..3f8237c17d09 100644
> --- a/drivers/net/ethernet/ti/icssg/icssg_config.c
> +++ b/drivers/net/ethernet/ti/icssg/icssg_config.c
> @@ -66,6 +66,9 @@
>  #define FDB_GEN_CFG1		0x60
>  #define SMEM_VLAN_OFFSET	8
>  #define SMEM_VLAN_OFFSET_MASK	GENMASK(25, 8)
> +#define FDB_HASH_SIZE_MASK	GENMASK(6, 3)
> +#define FDB_HASH_SIZE_SHIFT	3
> +#define FDB_HASH_SIZE		3

I am slightly confused about this.

The patch description says "The default FDB hash size used by the firmware
is 512 slots which is not aligned with the driver's configuration."
And above FDB_HASH_SIZE is 3, which is the value that the driver will
now set hash size to.

But table 6-1404 (on page 4049) of [1] describes 3 as setting
the FDB hash size to 512 slots. I would have expected a different
value based on my understanding of the patch description.

>  
>  #define FDB_GEN_CFG2		0x64
>  #define FDB_VLAN_EN		BIT(6)
> @@ -463,6 +466,8 @@ void icssg_init_emac_mode(struct prueth *prueth)
>  	/* Set VLAN TABLE address base */
>  	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK,
>  			   addr <<  SMEM_VLAN_OFFSET);
> +	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK,
> +			   FDB_HASH_SIZE << FDB_HASH_SIZE_SHIFT);
>  	/* Set enable VLAN aware mode, and FDBs for all PRUs */
>  	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, (FDB_PRU0_EN | FDB_PRU1_EN | FDB_HOST_EN));
>  	prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va +
> @@ -484,6 +489,8 @@ void icssg_init_fw_offload_mode(struct prueth *prueth)
>  	/* Set VLAN TABLE address base */
>  	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK,
>  			   addr <<  SMEM_VLAN_OFFSET);
> +	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK,
> +			   FDB_HASH_SIZE << FDB_HASH_SIZE_SHIFT);
>  	/* Set enable VLAN aware mode, and FDBs for all PRUs */
>  	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, FDB_EN_ALL);
>  	prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va +
> 
> base-commit: 68a052239fc4b351e961f698b824f7654a346091
> -- 
> 2.43.0
>
Re: [PATCH net] net: ti: icssg-prueth: Fix fdb hash size configuration
Posted by Meghana Malladi 2 months ago 
Hi Simon,

On 10/13/25 17:31, Simon Horman wrote:
> On Mon, Oct 13, 2025 at 02:29:25PM +0530, Meghana Malladi wrote:
>> The ICSSG driver does the initial FDB configuration which
>> includes setting the control registers. Other run time
>> management like learning is managed by the PRU's. The default
>> FDB hash size used by the firmware is 512 slots which is not
>> aligned with the driver's configuration. Update the driver
>> FDB config to fix it.
>>
>> Fixes: abd5576b9c57f ("net: ti: icssg-prueth: Add support for ICSSG switch firmware")
>> Signed-off-by: Meghana Malladi <m-malladi@ti.com>
>> ---
>>
>> Please refer trm [1] 6.4.14.12.17 section
>> on how the FDB config register gets configured.
>>
>> [1]: https://www.ti.com/lit/pdf/spruim2
> 
> Thanks for the link!
> And thanks to TI for publishing this document.
> 
>>
>>   drivers/net/ethernet/ti/icssg/icssg_config.c | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/ti/icssg/icssg_config.c b/drivers/net/ethernet/ti/icssg/icssg_config.c
>> index da53eb04b0a4..3f8237c17d09 100644
>> --- a/drivers/net/ethernet/ti/icssg/icssg_config.c
>> +++ b/drivers/net/ethernet/ti/icssg/icssg_config.c
>> @@ -66,6 +66,9 @@
>>   #define FDB_GEN_CFG1		0x60
>>   #define SMEM_VLAN_OFFSET	8
>>   #define SMEM_VLAN_OFFSET_MASK	GENMASK(25, 8)
>> +#define FDB_HASH_SIZE_MASK	GENMASK(6, 3)
>> +#define FDB_HASH_SIZE_SHIFT	3
>> +#define FDB_HASH_SIZE		3
> 
> I am slightly confused about this.
> 
> The patch description says "The default FDB hash size used by the firmware
> is 512 slots which is not aligned with the driver's configuration."
> And above FDB_HASH_SIZE is 3, which is the value that the driver will
> now set hash size to.
> 
> But table 6-1404 (on page 4049) of [1] describes 3 as setting
> the FDB hash size to 512 slots. I would have expected a different
> value based on my understanding of the patch description.
> 

Yes you are right. But if you re-check the same table 6-1404, there is
a reset field for FDB_HAS_SIZE which is 4, meaning 1024 slots.
Currently the driver is not updating this reset value from 4(1024 slots) 
to 3(512 slots), which is why the driver is not aligned with the 
firmware. This patch fixes this by updating the reset value to 512 slots.

Let me know if the commit message is not clear enough to convey this 
correctly. I will update it accordingly.

>>   
>>   #define FDB_GEN_CFG2		0x64
>>   #define FDB_VLAN_EN		BIT(6)
>> @@ -463,6 +466,8 @@ void icssg_init_emac_mode(struct prueth *prueth)
>>   	/* Set VLAN TABLE address base */
>>   	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK,
>>   			   addr <<  SMEM_VLAN_OFFSET);
>> +	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK,
>> +			   FDB_HASH_SIZE << FDB_HASH_SIZE_SHIFT);
>>   	/* Set enable VLAN aware mode, and FDBs for all PRUs */
>>   	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, (FDB_PRU0_EN | FDB_PRU1_EN | FDB_HOST_EN));
>>   	prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va +
>> @@ -484,6 +489,8 @@ void icssg_init_fw_offload_mode(struct prueth *prueth)
>>   	/* Set VLAN TABLE address base */
>>   	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK,
>>   			   addr <<  SMEM_VLAN_OFFSET);
>> +	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK,
>> +			   FDB_HASH_SIZE << FDB_HASH_SIZE_SHIFT);
>>   	/* Set enable VLAN aware mode, and FDBs for all PRUs */
>>   	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, FDB_EN_ALL);
>>   	prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va +
>>
>> base-commit: 68a052239fc4b351e961f698b824f7654a346091
>> -- 
>> 2.43.0
>>

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