The existing OPP table for PCIe is shared across different link
configurations such as data rates 8GT/s x2 and 16GT/s x1. These
configurations often operate at the same frequency, allowing them
to reuse the same OPP entries. However, 8GT/s and 16 GT/s may have
different RPMh votes which cannot be represented accurately when
sharing a single OPP.
To address this, introduce an `opp-level` to indicate the PCIe data
rate and uniquely differentiate OPP entries even when the frequency
is the same.
Although this platform does not currently suffer from this issue, the
change is introduced to support unification across platforms.
Append the opp level to name of the opp node to indicate both frequency
and level.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 79 ++++++++++++++++++++++++++----------
1 file changed, 57 insertions(+), 22 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 7724dba75db79a9e66a2c61e1ea3607bacfdf5bb..9e726f848d3ac1aa6769c5c5e336f53ce7df9046 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2027,39 +2027,52 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
pcie0_opp_table: opp-table {
compatible = "operating-points-v2";
- /* GEN 1 x1 */
- opp-2500000 {
+ /* 2.5 GT/s x1 */
+ opp-2500000-1 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
+ opp-level = <1>;
};
- /* GEN 1 x2 and GEN 2 x1 */
- opp-5000000 {
+ /* 2.5 GT/s x2 */
+ opp-5000000-1 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
+ opp-level = <1>;
};
- /* GEN 2 x2 */
- opp-10000000 {
+ /* 5 GT/s x1 */
+ opp-5000000-2 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ opp-level = <2>;
+ };
+
+ /* 5 GT/s x2 */
+ opp-10000000-2 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
+ opp-level = <2>;
};
- /* GEN 3 x1 */
- opp-8000000 {
+ /* 8 GT/s x1 */
+ opp-8000000-3 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <984500 1>;
+ opp-level = <3>;
};
- /* GEN 3 x2 */
- opp-16000000 {
+ /* 8 GT/s x2 */
+ opp-16000000-3 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <1969000 1>;
+ opp-level = <3>;
};
};
@@ -2194,46 +2207,68 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
pcie1_opp_table: opp-table {
compatible = "operating-points-v2";
- /* GEN 1 x1 */
- opp-2500000 {
+ /* 2.5 GT/s x1 */
+ opp-2500000-1 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
+ opp-level = <1>;
};
- /* GEN 1 x2 and GEN 2 x1 */
- opp-5000000 {
+ /* 2.5 GT/s x2 */
+ opp-5000000-1 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
+ opp-level = <1>;
};
- /* GEN 2 x2 */
- opp-10000000 {
+ /* 5 GT/s x1 */
+ opp-5000000-2 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ opp-level = <2>;
+ };
+
+ /* 5 GT/s x2 */
+ opp-10000000-2 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
+ opp-level = <2>;
};
- /* GEN 3 x1 */
- opp-8000000 {
+ /* 8 GT/s x1 */
+ opp-8000000-3 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <984500 1>;
+ opp-level = <3>;
+ };
+
+ /* 8 GT/s x2 */
+ opp-16000000-3 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ opp-level = <3>;
};
- /* GEN 3 x2 and GEN 4 x1 */
- opp-16000000 {
+ /* 16 GT/s x1 */
+ opp-16000000-4 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <1969000 1>;
+ opp-level = <4>;
};
- /* GEN 4 x2 */
- opp-32000000 {
+ /* 16 GT/s x2 */
+ opp-32000000-4 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <3938000 1>;
+ opp-level = <4>;
};
};
--
2.34.1