On Thu, Oct 09, 2025 at 09:41:51PM +0800, Yao Zihong wrote:
> Introduce RISCV_HWPROBE_EXT_ZICBOP to report presence of the Zicbop
> extension through hwprobe, and add RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE
> to expose the block size (in bytes) when Zicbop is supported.
>
> Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
> ---
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 948d2b34e94e..2f278c395af9 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,7 +8,7 @@
>
> #include <uapi/asm/hwprobe.h>
>
> -#define RISCV_HWPROBE_MAX_KEY 14
> +#define RISCV_HWPROBE_MAX_KEY 15
>
> static inline bool riscv_hwprobe_key_is_valid(__s64 key)
> {
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 5d30a4fae37a..9cc508be54c5 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -82,6 +82,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
> #define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
> #define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
> +#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 59)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> @@ -107,6 +108,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12
> #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13
> #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14
> +#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15
> /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>
> /* Flags */
> --
> 2.47.2
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>