From: Joel Fernandes <joelagnelf@nvidia.com>

This will be needed by both the GSP boot code as well as GSP resume code
in the sequencer.

Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
---
 drivers/gpu/nova-core/falcon.rs | 9 +++++++++
 drivers/gpu/nova-core/regs.rs   | 6 ++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 185ed6d1cfb8..01869b8deb8a 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -515,4 +515,13 @@ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool {
         let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID);
         cpuctl.active_stat()
     }
+
+    /// Write the application version to the OS register.
+    #[expect(dead_code)]
+    pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) -> Result<()> {
+        regs::NV_PFALCON_FALCON_OS::default()
+            .set_value(app_version)
+            .write(bar, &E::ID);
+        Ok(())
+    }
 }
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 3bd1bddb16bb..6eda5c44c599 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -215,6 +215,12 @@ pub(crate) fn vga_workspace_addr(self) -> Option<u64> {
     31:0    value as u32;
 });
 
+// Used to store version information about the firmware running
+// on the Falcon processor.
+register!(NV_PFALCON_FALCON_OS @ PFalconBase[0x00000080] {
+    31:0    value as u32;
+});
+
 register!(NV_PFALCON_FALCON_RM @ PFalconBase[0x00000084] {
     31:0    value as u32;
 });
-- 
2.50.1

On Wed, 2025-10-08 at 11:12 +1100, Alistair Popple wrote:
> +
> +    /// Write the application version to the OS register.
> +    #[expect(dead_code)]
> +    pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) -> Result<()> {
> +        regs::NV_PFALCON_FALCON_OS::default()
> +            .set_value(app_version)
> +            .write(bar, &E::ID);
> +        Ok(())
> +    }

I should have noticed this in v3, but why return Result here?  This is just like is_riscv_active
-- this function cannot fail.

On 2025-10-08 at 14:21 +1100, Timur Tabi <ttabi@nvidia.com> wrote...
> On Wed, 2025-10-08 at 11:12 +1100, Alistair Popple wrote:
> > +
> > +    /// Write the application version to the OS register.
> > +    #[expect(dead_code)]
> > +    pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) -> Result<()> {
> > +        regs::NV_PFALCON_FALCON_OS::default()
> > +            .set_value(app_version)
> > +            .write(bar, &E::ID);
> > +        Ok(())
> > +    }
> 
> I should have noticed this in v3, but why return Result here?  This is just like is_riscv_active
> -- this function cannot fail.

Oh phooey. I recall noticing this but must've missed it when splitting the
fixes. There will almost certainly be a v5 so will fix it then. Thanks.

> On Oct 7, 2025, at 11:21 PM, Timur Tabi <ttabi@nvidia.com> wrote:
> 
> On Wed, 2025-10-08 at 11:12 +1100, Alistair Popple wrote:
>> +
>> +    /// Write the application version to the OS register.
>> +    #[expect(dead_code)]
>> +    pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) -> Result<()> {
>> +        regs::NV_PFALCON_FALCON_OS::default()
>> +            .set_value(app_version)
>> +            .write(bar, &E::ID);
>> +        Ok(())
>> +    }
> 
> I should have noticed this in v3, but why return Result here?  This is just like is_riscv_active
> -- this function cannot fail.

Ack. Let us fix. IIRC, it is a remnant from a time when the function could fail.

I can submit a fixup to squash if there are no other changes to the series.

Thanks.