Add SD Card host controller for sm8750 soc.
Signed-off-by: Sarthak Garg <sarthak.garg@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 63 ++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index a82d9867c7cb..dce70443f719 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -2060,6 +2060,55 @@ ice: crypto@1d88000 {
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+
+ interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ iommus = <&apps_smmu 0x540 0x0>;
+ dma-coherent;
+
+ bus-width = <4>;
+ max-sd-hs-hz = <37500000>;
+
+ resets = <&gcc GCC_SDCC2_BCR>;
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
@@ -3121,6 +3170,13 @@ data-pins {
drive-strength = <2>;
bias-pull-up;
};
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
sdc2_default: sdc2-default-state {
@@ -3141,6 +3197,13 @@ data-pins {
drive-strength = <10>;
bias-pull-up;
};
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
};
--
2.34.1On 10/7/25 7:44 AM, Sarthak Garg wrote:
> Add SD Card host controller for sm8750 soc.
>
> Signed-off-by: Sarthak Garg <sarthak.garg@oss.qualcomm.com>
> ---
[...]
> + sdhc_2: mmc@8804000 {
> + compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0 0x08804000 0 0x1000>;
> +
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
One a line, please
> +
> + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> + <&gcc GCC_SDCC2_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
Please align the '<'s
> + clock-names = "iface", "core", "xo";
One a line, please
> +
> + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
and here
> +
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + operating-points-v2 = <&sdhc2_opp_table>;
> +
> + qcom,dll-config = <0x0007442c>;
> + qcom,ddr-config = <0x80040868>;
> +
> + iommus = <&apps_smmu 0x540 0x0>;
> + dma-coherent;
> +
> + bus-width = <4>;
> + max-sd-hs-hz = <37500000>;
> +
> + resets = <&gcc GCC_SDCC2_BCR>;
> + status = "disabled";
A \n before 'status' is customary
> +
> + sdhc2_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-202000000 {
> + opp-hz = /bits/ 64 <202000000>;
> + required-opps = <&rpmhpd_opp_nom>;
This can work at SVS_L1
Konrad
On 10/8/2025 5:47 PM, Konrad Dybcio wrote:
> On 10/7/25 7:44 AM, Sarthak Garg wrote:
>> Add SD Card host controller for sm8750 soc.
>>
>> Signed-off-by: Sarthak Garg <sarthak.garg@oss.qualcomm.com>
>> ---
> [...]
>
>> + sdhc_2: mmc@8804000 {
>> + compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5";
>> + reg = <0 0x08804000 0 0x1000>;
>> +
>> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hc_irq", "pwr_irq";
> One a line, please
Sure will update it in V2.
>> +
>> + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
>> + <&gcc GCC_SDCC2_APPS_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>;
> Please align the '<'s
Sure will update it in V2.
>> + clock-names = "iface", "core", "xo";
> One a line, please
Sure will update it in V2.
>> +
>> + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
>> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
> and here
Sure will update it in V2.
>
>> +
>> + power-domains = <&rpmhpd RPMHPD_CX>;
>> + operating-points-v2 = <&sdhc2_opp_table>;
>> +
>> + qcom,dll-config = <0x0007442c>;
>> + qcom,ddr-config = <0x80040868>;
>> +
>> + iommus = <&apps_smmu 0x540 0x0>;
>> + dma-coherent;
>> +
>> + bus-width = <4>;
>> + max-sd-hs-hz = <37500000>;
>> +
>> + resets = <&gcc GCC_SDCC2_BCR>;
>> + status = "disabled";
> A \n before 'status' is customary
Sure will update it in V2.
>
>> +
>> + sdhc2_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-100000000 {
>> + opp-hz = /bits/ 64 <100000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-202000000 {
>> + opp-hz = /bits/ 64 <202000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
> This can work at SVS_L1
>
> Konrad
Sure will update to rpmhpd_opp_svs_l1 in V2.
Regards,
Sarthak
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