Document the DWC3 USB bindings for Google Tensor SoCs.
Signed-off-by: Roy Luo <royluo@google.com>
---
.../bindings/usb/google,snps-dwc3.yaml | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml
new file mode 100644
index 000000000000..3e8bcc0c2cef
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2025, Google LLC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/google,snps-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google DWC3 USB SoC Controller
+
+maintainers:
+ - Roy Luo <royluo@google.com>
+
+description:
+ Describes the Google DWC3 USB block, based on Synopsys DWC3 IP.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - google,lga-dwc3
+ - const: google,snps-dwc3
+
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ reg-names:
+ description: |
+ The following memory regions must present:
+ - dwc3_core: Core DWC3 IP registers.
+ - host_cfg_csr: Hibernation control registers.
+ - usbint_csr: Hibernation interrupt registers.
+ items:
+ - const: dwc3_core
+ - const: host_cfg_csr
+ - const: usbint_csr
+
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+ interrupt-names:
+ description: |
+ The following interrupts must present:
+ - dwc_usb3: Core DWC3 interrupt.
+ - hs_pme_irq: High speed remote wakeup interrupt for hibernation.
+ - ss_pme_irq: Super speed remote wakeup interrupt for hibernation.
+ items:
+ - const: dwc_usb3
+ - const: hs_pme_irq
+ - const: ss_pme_irq
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ clock-names:
+ minItems: 3
+ maxItems: 3
+
+ resets:
+ minItems: 5
+ maxItems: 5
+
+ reset-names:
+ items:
+ - const: usbc_non_sticky
+ - const: usbc_sticky
+ - const: usb_drd_bus
+ - const: u2phy_apb
+ - const: usb_top_csr
+
+ power-domains:
+ minItems: 2
+ maxItems: 2
+
+ power-domain-names:
+ description: |
+ The following power domain must present:
+ - usb_psw_pd: The child power domain of usb_top_pd. Turning it on puts the controller
+ into full power state, turning it off puts the controller into power
+ gated state.
+ - usb_top_pd: The parent power domain of usb_psw_pd. Turning it on puts the controller
+ into power gated state, turning it off completely shuts off the
+ controller.
+ items:
+ - const: usb_psw_pd
+ - const: usb_top_pd
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - resets
+ - reset-names
+ - power-domains
+ - power-domain-names
+
+allOf:
+ - $ref: snps,dwc3-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb@c400000 {
+ compatible = "google,lga-dwc3", "google,snps-dwc3";
+ reg = <0 0x0c400000 0 0xd060>, <0 0x0c450000 0 0x14>, <0 0x0c450020 0 0x8>;
+ reg-names = "dwc3_core", "host_cfg_csr", "usbint_csr";
+ interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dwc_usb3", "hs_pme_irq", "ss_pme_irq";
+ clocks = <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_clk>,
+ <&hsion_u2phy_apb_clk>;
+ clock-names = "usbc_non_sticky", "usbc_sticky", "u2phy_apb";
+ resets = <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usbc_sticky>,
+ <&hsion_resets_usb_drd_bus>, <&hsion_resets_u2phy_apb>,
+ <&hsion_resets_usb_top_csr>;
+ reset-names = "usbc_non_sticky", "usbc_sticky",
+ "usb_drd_bus", "u2phy_apb",
+ "usb_top_csr";
+ power-domains = <&hsio_n_usb_psw_pd>, <&hsio_n_usb_pd>;
+ power-domain-names = "usb_psw_pd", "usb_top_pd";
+ phys = <&usb_phy 0>;
+ phy-names = "usb2-phy";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,gfladj-refclk-lpm-sel-quirk;
+ snps,incr-burst-type-adjustment = <4>;
+ };
+ };
+...
--
2.51.0.618.g983fd99d29-googOn 07/10/2025 08:21, Roy Luo wrote: > Document the DWC3 USB bindings for Google Tensor SoCs. > > Signed-off-by: Roy Luo <royluo@google.com> > --- > .../bindings/usb/google,snps-dwc3.yaml | 144 ++++++++++++++++++ > 1 file changed, 144 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml > > diff --git a/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml > new file mode 100644 > index 000000000000..3e8bcc0c2cef > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml > @@ -0,0 +1,144 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (c) 2025, Google LLC > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/google,snps-dwc3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Google DWC3 USB SoC Controller > + > +maintainers: > + - Roy Luo <royluo@google.com> > + > +description: > + Describes the Google DWC3 USB block, based on Synopsys DWC3 IP. > + > +properties: > + compatible: > + items: > + - enum: > + - google,lga-dwc3 > + - const: google,snps-dwc3 There is no such soc as snps, so you grossly misuse other company name as name of SoC. Neither lga. Otherwise please point me to the top-level bindings describing that SoC. You need to better describe the hardware here - why this is something completely different than GS which. Or switch to existing bindings and existing drivers. Did you align this with Peter Griffin? Best regards, Krzysztof
Hi Krzysztof & Roy, Firstly thanks Roy for your patches, it's great to see more Tensor support being posted upstream! On Tue, 7 Oct 2025 at 01:44, Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 07/10/2025 08:21, Roy Luo wrote: > > Document the DWC3 USB bindings for Google Tensor SoCs. > > > > Signed-off-by: Roy Luo <royluo@google.com> > > --- > > .../bindings/usb/google,snps-dwc3.yaml | 144 ++++++++++++++++++ > > 1 file changed, 144 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml > > > > diff --git a/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml > > new file mode 100644 > > index 000000000000..3e8bcc0c2cef > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml > > @@ -0,0 +1,144 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (c) 2025, Google LLC > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/usb/google,snps-dwc3.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Google DWC3 USB SoC Controller > > + > > +maintainers: > > + - Roy Luo <royluo@google.com> > > + > > +description: > > + Describes the Google DWC3 USB block, based on Synopsys DWC3 IP. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - google,lga-dwc3 > > + - const: google,snps-dwc3 > > > There is no such soc as snps, so you grossly misuse other company name > as name of SoC. Neither lga. Otherwise please point me to the top-level > bindings describing that SoC. > > You need to better describe the hardware here - why this is something > completely different than GS which. Or switch to existing bindings and > existing drivers. Did you align this with Peter Griffin? I think (from what I've seen at least) this is the first submission for drivers in the Tensor G5 SoC used in Pixel 10 devices (which as I understand it isn't based on any Samsung IP). Hence the new drivers, bindings etc. However the issue is that none of the other base SoC drivers on which this driver depends currently exist upstream (like clocks, reset driver, power domains, pinctrl etc). So it's very hard to reason about the correctness or otherwise of this submission. It is also likely that when those drivers are upstreamed things could change in the review process, to how it looks today in the downstream kernel. So in summary I think to progress with this we need to get the base Tensor G5 SoC drivers merged first (e.g. boot to console with pinctrl, basic clock support, reset driver etc). Then we can start adding in some of the other peripherals like i2c/spi/usb etc and build up the mainline support from there. Thanks, Peter.
On 07/10/2025 18:09, Peter Griffin wrote: > Hi Krzysztof & Roy, > > Firstly thanks Roy for your patches, it's great to see more Tensor > support being posted upstream! > > On Tue, 7 Oct 2025 at 01:44, Krzysztof Kozlowski <krzk@kernel.org> wrote: >> >> On 07/10/2025 08:21, Roy Luo wrote: >>> Document the DWC3 USB bindings for Google Tensor SoCs. >>> >>> Signed-off-by: Roy Luo <royluo@google.com> >>> --- >>> .../bindings/usb/google,snps-dwc3.yaml | 144 ++++++++++++++++++ >>> 1 file changed, 144 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml >>> new file mode 100644 >>> index 000000000000..3e8bcc0c2cef >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml >>> @@ -0,0 +1,144 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> +# Copyright (c) 2025, Google LLC >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/usb/google,snps-dwc3.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Google DWC3 USB SoC Controller >>> + >>> +maintainers: >>> + - Roy Luo <royluo@google.com> >>> + >>> +description: >>> + Describes the Google DWC3 USB block, based on Synopsys DWC3 IP. >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - enum: >>> + - google,lga-dwc3 >>> + - const: google,snps-dwc3 >> >> >> There is no such soc as snps, so you grossly misuse other company name >> as name of SoC. Neither lga. Otherwise please point me to the top-level >> bindings describing that SoC. >> >> You need to better describe the hardware here - why this is something >> completely different than GS which. Or switch to existing bindings and >> existing drivers. Did you align this with Peter Griffin? > > I think (from what I've seen at least) this is the first submission > for drivers in the Tensor G5 SoC used in Pixel 10 devices (which as I > understand it isn't based on any Samsung IP). Hence the new drivers, > bindings etc. That could explain a lot. I would be happy to see background of hardware in the bindings commit msg and the cover letter. > > However the issue is that none of the other base SoC drivers on which > this driver depends currently exist upstream (like clocks, reset > driver, power domains, pinctrl etc). So it's very hard to reason about > the correctness or otherwise of this submission. It is also likely > that when those drivers are upstreamed things could change in the > review process, to how it looks today in the downstream kernel. Bindings and drivers can be contributed without core SoC support, but then please describe the hardware (SoC) here. Having core support posted earlier is of course preferred, but I think not a requirement. Anyway, compatibles and all commit messages in this patchset are too generic and need to reflect this actual SoC, not "Tensor" because we already have a Tensor with USB. So basically based on existing support all this patchset would be redundant, right? :) Best regards, Krzysztof
On Tue, Oct 7, 2025 at 7:18 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 07/10/2025 18:09, Peter Griffin wrote: > > Hi Krzysztof & Roy, > > > > Firstly thanks Roy for your patches, it's great to see more Tensor > > support being posted upstream! > > > > On Tue, 7 Oct 2025 at 01:44, Krzysztof Kozlowski <krzk@kernel.org> wrote: > >> > >> On 07/10/2025 08:21, Roy Luo wrote: > >>> Document the DWC3 USB bindings for Google Tensor SoCs. > >>> > >>> Signed-off-by: Roy Luo <royluo@google.com> > >>> --- > >>> .../bindings/usb/google,snps-dwc3.yaml | 144 ++++++++++++++++++ > >>> 1 file changed, 144 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml > >>> new file mode 100644 > >>> index 000000000000..3e8bcc0c2cef > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml > >>> @@ -0,0 +1,144 @@ > >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > >>> +# Copyright (c) 2025, Google LLC > >>> +%YAML 1.2 > >>> +--- > >>> +$id: http://devicetree.org/schemas/usb/google,snps-dwc3.yaml# > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>> + > >>> +title: Google DWC3 USB SoC Controller > >>> + > >>> +maintainers: > >>> + - Roy Luo <royluo@google.com> > >>> + > >>> +description: > >>> + Describes the Google DWC3 USB block, based on Synopsys DWC3 IP. > >>> + > >>> +properties: > >>> + compatible: > >>> + items: > >>> + - enum: > >>> + - google,lga-dwc3 > >>> + - const: google,snps-dwc3 > >> > >> > >> There is no such soc as snps, so you grossly misuse other company name > >> as name of SoC. Neither lga. Otherwise please point me to the top-level > >> bindings describing that SoC. > >> > >> You need to better describe the hardware here - why this is something > >> completely different than GS which. Or switch to existing bindings and > >> existing drivers. Did you align this with Peter Griffin? > > > > I think (from what I've seen at least) this is the first submission > > for drivers in the Tensor G5 SoC used in Pixel 10 devices (which as I > > understand it isn't based on any Samsung IP). Hence the new drivers, > > bindings etc. > > > That could explain a lot. I would be happy to see background of hardware > in the bindings commit msg and the cover letter. > > > > > However the issue is that none of the other base SoC drivers on which > > this driver depends currently exist upstream (like clocks, reset > > driver, power domains, pinctrl etc). So it's very hard to reason about > > the correctness or otherwise of this submission. It is also likely > > that when those drivers are upstreamed things could change in the > > review process, to how it looks today in the downstream kernel. > > > Bindings and drivers can be contributed without core SoC support, but > then please describe the hardware (SoC) here. Having core support posted > earlier is of course preferred, but I think not a requirement. > > Anyway, compatibles and all commit messages in this patchset are too > generic and need to reflect this actual SoC, not "Tensor" because we > already have a Tensor with USB. So basically based on existing support > all this patchset would be redundant, right? :) > > Best regards, > Krzysztof Hi Krzysztof and Peter, My apologies for not providing the full context on the SoC supported in this series. Thanks to Peter for clarifying; yes, the Tensor G5 SoC is a new generation of Google silicon that is significantly different from previous generations which are based on Samsung/Exynos IP. This necessitates new bindings and drivers for the G5 and future generations, and I will ensure this is clearly detailed in the next patch set's cover letter and commit message. I acknowledge that the core SoC support (clocks, reset, etc.) for G5 is still missing from upstream. We do have plans to push this forward, but I don't have a firm timeline yet. Thanks for confirming that this won't be a show stopper for this patchset. Thanks, Roy Luo
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