On Thu, 2 Oct 2025 at 11:09, James Clark <james.clark@linaro.org> wrote:
>
> TRCSYNCPR.PERIOD is the only functional part of TRCSYNCPR and it only
> has 5 valid bits so it can be stored in a u8.
>
> Signed-off-by: James Clark <james.clark@linaro.org>
> ---
> drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 13ec9ecef46f..eda3a6d2e8e2 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -825,7 +825,6 @@ struct etmv4_config {
> u32 eventctrl1;
> u32 stall_ctrl;
> u32 ts_ctrl;
> - u32 syncfreq;
> u32 ccctlr;
> u32 bb_ctrl;
> u32 vinst_ctrl;
> @@ -833,6 +832,7 @@ struct etmv4_config {
> u32 vissctlr;
> u32 vipcssctlr;
> u8 seq_idx;
> + u8 syncfreq;
> u32 seq_ctrl[ETM_MAX_SEQ_STATES];
> u32 seq_rst;
> u32 seq_state;
>
> --
> 2.34.1
>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK