Add 'reg' and 'clocks' properties to enable QoS configuration. These
properties enable access to QoS registers and necessary clocks for
configuration.
QoS configuration is essential for ensuring that latency sensitive
components such as CPUs and multimedia engines receive prioritized
access to memory and interconnect resources. This helps to manage
bandwidth and latency across subsystems, improving system responsiveness
and performance in concurrent workloads.
Both 'reg' and 'clocks' properties are optional. If either is missing,
QoS configuration will be skipped. This behavior is controlled by the
'qos_requires_clocks' flag in the driver, which ensures that QoS
configuration is bypassed when required clocks are not defined.
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
---
.../interconnect/qcom,sa8775p-rpmh.yaml | 50 ++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
index db19fd5c5708..71428d2cce18 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
@@ -33,18 +33,66 @@ properties:
- qcom,sa8775p-pcie-anoc
- qcom,sa8775p-system-noc
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 5
+
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-aggre1-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS PHY AXI clock
+ - description: aggre QUP PRIM AXI clock
+ - description: aggre USB2 PRIM AXI clock
+ - description: aggre USB3 PRIM AXI clock
+ - description: aggre USB3 SEC AXI clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-aggre2-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS CARD AXI clock
+ - description: RPMH CC IPA clock
unevaluatedProperties: false
examples:
- |
- aggre1_noc: interconnect-aggre1-noc {
+ #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+ clk_virt: interconnect-clk-virt {
+ compatible = "qcom,sa8775p-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16c0000 {
compatible = "qcom,sa8775p-aggre1-noc";
+ reg = <0x016c0000 0x18080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
};
--
2.17.1On Wed, Oct 01, 2025 at 01:03:42PM +0530, Odelu Kukatla wrote:
> Add 'reg' and 'clocks' properties to enable QoS configuration. These
> properties enable access to QoS registers and necessary clocks for
> configuration.
>
> QoS configuration is essential for ensuring that latency sensitive
> components such as CPUs and multimedia engines receive prioritized
> access to memory and interconnect resources. This helps to manage
> bandwidth and latency across subsystems, improving system responsiveness
> and performance in concurrent workloads.
>
> Both 'reg' and 'clocks' properties are optional. If either is missing,
> QoS configuration will be skipped. This behavior is controlled by the
> 'qos_requires_clocks' flag in the driver, which ensures that QoS
> configuration is bypassed when required clocks are not defined.
>
> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
> ---
> .../interconnect/qcom,sa8775p-rpmh.yaml | 50 ++++++++++++++++++-
> 1 file changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
> index db19fd5c5708..71428d2cce18 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
> @@ -33,18 +33,66 @@ properties:
> - qcom,sa8775p-pcie-anoc
> - qcom,sa8775p-system-noc
>
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 5
> +
> required:
> - compatible
>
> allOf:
> - $ref: qcom,rpmh-common.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sa8775p-aggre1-noc
> + then:
> + properties:
> + clocks:
> + items:
> + - description: aggre UFS PHY AXI clock
> + - description: aggre QUP PRIM AXI clock
> + - description: aggre USB2 PRIM AXI clock
> + - description: aggre USB3 PRIM AXI clock
> + - description: aggre USB3 SEC AXI clock
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sa8775p-aggre2-noc
> + then:
> + properties:
> + clocks:
> + items:
> + - description: aggre UFS CARD AXI clock
> + - description: RPMH CC IPA clock
>
> unevaluatedProperties: false
>
> examples:
> - |
> - aggre1_noc: interconnect-aggre1-noc {
> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> + clk_virt: interconnect-clk-virt {
> + compatible = "qcom,sa8775p-clk-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + aggre1_noc: interconnect@16c0000 {
> compatible = "qcom,sa8775p-aggre1-noc";
> + reg = <0x016c0000 0x18080>;
> #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
> };
> --
> 2.17.1
>
On Wed, 01 Oct 2025 13:03:42 +0530, Odelu Kukatla wrote: > Add 'reg' and 'clocks' properties to enable QoS configuration. These > properties enable access to QoS registers and necessary clocks for > configuration. > > QoS configuration is essential for ensuring that latency sensitive > components such as CPUs and multimedia engines receive prioritized > access to memory and interconnect resources. This helps to manage > bandwidth and latency across subsystems, improving system responsiveness > and performance in concurrent workloads. > > Both 'reg' and 'clocks' properties are optional. If either is missing, > QoS configuration will be skipped. This behavior is controlled by the > 'qos_requires_clocks' flag in the driver, which ensures that QoS > configuration is bypassed when required clocks are not defined. > > Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> > --- > .../interconnect/qcom,sa8775p-rpmh.yaml | 50 ++++++++++++++++++- > 1 file changed, 49 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
© 2016 - 2026 Red Hat, Inc.