Modern AMD CPUs do not support segment limit checks in 64-bit mode
(i.e. EFER.LMSLE must be zero). Do not allow a guest to set EFER.LMSLE
on a CPU that requires the bit to be zero.

For backwards compatibility, allow EFER.LMSLE to be set on CPUs that
support segment limit checks in 64-bit mode, even though KVM's
implementation of the feature is incomplete (e.g. KVM's emulator does
not enforce segment limits in 64-bit mode).

Fixes: eec4b140c924 ("KVM: SVM: Allow EFER.LMSLE to be set with nested svm")

Signed-off-by: Jim Mattson <jmattson@google.com>
---
 arch/x86/kvm/svm/svm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 1bfebe40854f..78d0fc85d0bd 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -5351,7 +5351,9 @@ static __init int svm_hardware_setup(void)
 
 	if (nested) {
 		pr_info("Nested Virtualization enabled\n");
-		kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
+		kvm_enable_efer_bits(EFER_SVME);
+		if (!boot_cpu_has(X86_FEATURE_EFER_LMSLE_MBZ))
+			kvm_enable_efer_bits(EFER_LMSLE);
 
 		r = nested_svm_init_msrpm_merge_offsets();
 		if (r)
-- 
2.51.0.618.g983fd99d29-goog

On Tue, Sep 30, 2025 at 05:14:08PM -0700, Jim Mattson wrote:
> Modern AMD CPUs do not support segment limit checks in 64-bit mode
> (i.e. EFER.LMSLE must be zero). Do not allow a guest to set EFER.LMSLE
> on a CPU that requires the bit to be zero.

If anyone is as curious as I was, the bit seemingly started being set on
Milan. Rome (and supposedly older CPUs) support EFER.LMSLE.

> 
> For backwards compatibility, allow EFER.LMSLE to be set on CPUs that
> support segment limit checks in 64-bit mode, even though KVM's
> implementation of the feature is incomplete (e.g. KVM's emulator does
> not enforce segment limits in 64-bit mode).
> 
> Fixes: eec4b140c924 ("KVM: SVM: Allow EFER.LMSLE to be set with nested svm")
> 
> Signed-off-by: Jim Mattson <jmattson@google.com>
> ---
>  arch/x86/kvm/svm/svm.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> index 1bfebe40854f..78d0fc85d0bd 100644
> --- a/arch/x86/kvm/svm/svm.c
> +++ b/arch/x86/kvm/svm/svm.c
> @@ -5351,7 +5351,9 @@ static __init int svm_hardware_setup(void)
>  
>  	if (nested) {
>  		pr_info("Nested Virtualization enabled\n");
> -		kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
> +		kvm_enable_efer_bits(EFER_SVME);
> +		if (!boot_cpu_has(X86_FEATURE_EFER_LMSLE_MBZ))
> +			kvm_enable_efer_bits(EFER_LMSLE);
>  
>  		r = nested_svm_init_msrpm_merge_offsets();
>  		if (r)
> -- 
> 2.51.0.618.g983fd99d29-goog
>

On Tue, Sep 30, 2025 at 05:14:08PM -0700, Jim Mattson wrote:
> Modern AMD CPUs do not support segment limit checks in 64-bit mode
> (i.e. EFER.LMSLE must be zero). Do not allow a guest to set EFER.LMSLE
> on a CPU that requires the bit to be zero.
> 
> For backwards compatibility, allow EFER.LMSLE to be set on CPUs that
> support segment limit checks in 64-bit mode, even though KVM's
> implementation of the feature is incomplete (e.g. KVM's emulator does
> not enforce segment limits in 64-bit mode).
> 
> Fixes: eec4b140c924 ("KVM: SVM: Allow EFER.LMSLE to be set with nested svm")
> 
> Signed-off-by: Jim Mattson <jmattson@google.com>

Reviewed-by: Yosry Ahmed <yosry.ahmed@linux.dev>

> ---
>  arch/x86/kvm/svm/svm.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> index 1bfebe40854f..78d0fc85d0bd 100644
> --- a/arch/x86/kvm/svm/svm.c
> +++ b/arch/x86/kvm/svm/svm.c
> @@ -5351,7 +5351,9 @@ static __init int svm_hardware_setup(void)
>  
>  	if (nested) {
>  		pr_info("Nested Virtualization enabled\n");
> -		kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
> +		kvm_enable_efer_bits(EFER_SVME);
> +		if (!boot_cpu_has(X86_FEATURE_EFER_LMSLE_MBZ))
> +			kvm_enable_efer_bits(EFER_LMSLE);
>  
>  		r = nested_svm_init_msrpm_merge_offsets();
>  		if (r)
> -- 
> 2.51.0.618.g983fd99d29-goog
>