From: Chuan Liu <chuan.liu@amlogic.com>
Add the PLL clock controller dt-bindings for Amlogic A4 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
.../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++++++++++++++++++++++
include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 ++++++
2 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a4-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a4-pll-clkc.yaml
new file mode 100644
index 000000000000..dafad7bd4407
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a4-pll-clkc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a4-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A4 series PLL Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Chuan Liu <chuan.liu@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,a4-pll-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input oscillator
+ - description: input fix pll
+
+ clock-names:
+ items:
+ - const: xtal
+ - const: fix
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,a4-scmi-clkc.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@8000 {
+ compatible = "amlogic,a4-pll-clkc";
+ reg = <0x0 0x8000 0x0 0x110>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_FIXED_PLL>;
+ clock-names = "xtal",
+ "fix";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,a4-pll-clkc.h b/include/dt-bindings/clock/amlogic,a4-pll-clkc.h
new file mode 100644
index 000000000000..0950dcd68e0a
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a4-pll-clkc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A4_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_A4_PLL_CLKC_H
+
+#define CLKID_GP0_PLL_DCO 0
+#define CLKID_GP0_PLL 1
+#define CLKID_HIFI_PLL_DCO 2
+#define CLKID_HIFI_PLL 3
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A4_PLL_CLKC_H */
--
2.42.0